參數(shù)資料
型號(hào)： AS9C25256M2018L-166BC
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： TERM. F/O CABLE ST-SC/ DPLX/RISER/5M/GREEN
中文描述： 256K X 18 DUAL-PORT SRAM, 10 ns, PBGA256
封裝： BGA-256
文件頁數(shù)： 8/30頁
文件大?。?/td> 1100K
代理商： AS9C25256M2018L-166BC
AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 8 of 30
Byte control truth table
[1,2,3,4,5]
Notes:
1. L = low, H = high
2. CE0 = L, CE1 = H (Chip in Select mode)
3. R/W = H for a Read operation, R/W = L for a Write operation
4. Byte 1 - DQ[17:9], Byte 0 - DQ[8:0]
5. More than one byte enable may be simultaneously asserted
Read/write control truth table
[1,4]
Notes:
1. L = low, H = high, X = don't care
2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H)
3. BE
n
refers to any one of the 2 byte controls [n = 1 or 0] and DQ
n
refers to the corresponding Byte
4. Snooze de-asserted (ZZ=L)
5. True in flow-through mode. For Pipeline mode there will be a 1 cycle latency [refer timing diagrams]
6. For a write command issued before the completion of a read command, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.
7. All DQs are tristated on power-up
8. OE should be asserted (OE = L) (Refer Read timing waveform)
9. In pipeline mode the DQs are HighZ-ed in the same cycle if R/W=L
Counter control truth table
[1,2,5,6]
Notes:
1. L = low, H = high, X = don't care
2. Cycle can be Read, Write or Deselect (Controlled by appropriate setting of R/W, CE0, CE1 and BE
n
)
3. ADS, INC, RPT are independent of all other memory controls including R/W, CE0,CE1 and BE
n
(i.e Counter works independent of R/W, CE0,CE1 and BE
n
)
4. The 'Mirror register' used for the Repeat operation is loaded with External address during every valid ADS access. “Am” refers to the mirror register content.
5. Clock to the counter is disabled during Snooze mode (True for both ports).
6. The counter and the mirror registers are not initialized on Power-up (refer Counter description).
BE1
H
H
L
BE0
H
L
H
CLK
L to H
L to H
L to H
Mode
All Bytes Deselected - NOP
Read or Write Byte 0
Read or Write Byte 1
CE
[2]
H
L
R/W
X
X
BE
n[3]
X
H
CLK
L to H
L to H
Operation
DQ
n
[0:8]
[3,7]
Hi-Z
[5,9]
Hi-Z
[5,9]
Din
[6]
Qout
[5,8]
Chip Deselect
Byte Deselect
L
L
L
L to H
Byte Write
L
H
L
L to H
Byte Read
CLK
L to H
L to H
L to H
L to H
ADS
[3]
L
H
H
X
INC
[3]
X
L
H
X
RPT
[3]
H
H
H
L
External
Address
An
X
X
X
Previous
Address
Accessed
X
An
An
X
Mirror
Register
Content
[4]
An
Am
Am
Am
Address
Accessed
An
An + 1
An
Am
Operation
Load
[4]
Increment
Hold
Repeat
相關(guān)PDF資料
PDF描述
AS9C25512M2018L-166BI TERM. F/O CABLE ST-SC/ DPLX/RISER/10M/GREEN
AS9C25256M2018L-166BI TERM. F/O CABLE ST-SC/ DPLX/RISER/1M/YELLOW
AS9C25512M2018L-166FC TERM. F/O CABLE ST-SC/ DPLX/RISER/2M/YELLOW
AS9C25256M2018L-166FC TERM. F/O CABLE ST-SC/ DPLX/RISER/3M/YELLOW
AS9C25512M2018L-166FI TERM. F/O CABLE ST-SC/ DPLX/RISER/5M/YELLOW
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS9C25256M2018L-166BI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-166FC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-166FI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-166TC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
AS9C25256M2018L-166TI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
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