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參數(shù)資料
| 型號： | AS9C25256M2018L-133TI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | TERM. F/O CABLE ST-SC/ DPLX/RISER/2M/GREEN |
| 中文描述： | 256K X 18 DUAL-PORT SRAM, 12 ns, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大小： | 1100K |
| 代理商： | AS9C25256M2018L-133TI |
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AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 12 of 30
AC timing characteristics
[1,2,5,6]
(VDD = 2.5 ± 100mV)
Parameter
Notes:
1. All timings are same for both ports.
2. These values are valid for either level of VDDQ (2.5V/3.3V)
3. A particular port will operate in Pipeline output mode if PL/FT = VDD and in flow-through output mode if PL/FT = 0V. Each port can independently operate in any of these
modes.
4. Output Enable (OE) is an asynchronous input.
5. PL/FT and OPT should be treated as DC signals and should reach steady state before normal operation.
6. Refer AC Test Conditions to view the test conditions used for these measurements.
7. This parameter has to be taken care to avoid collision during simultaneous memory access of the same location.
8. To avoid bus contention, at a given voltage and temperature t
LZC
is more than t
HZC
(True in both Pipeline and flow-through output mode).
Symbol
-250
-200
-166
-133
Unit Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Clock
Cycle Time (Pipeline)
Clock High Pulse Width (Pipeline)
Clock Low Pulse Width (Pipeline)
Cycle Time (Flow-Through)
Clock High Pulse Width (Flow-Through)
Clock Low Pulse Width (Flow-Through)
Output
Clock access time (Pipeline)
Output Data Hold from Clock High (Pipeline)
Clock High to Output Low-Z (Pipeline)
Clock High to Output High-Z (Pipeline)
Clock access time (Flow-Through)
Output Data Hold from Clock High (Flow-Through)
Clock High to Output Low-Z (Flow-Through)
Clock High to Output High-Z (Flow-Through)
Output Enable to Data Valid
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Setup
Address Setup to Clock High
Chip Enable Setup to Clock High
Byte Enable Setup to Clock High
R/W
Setup to Clock High
Input Data Setup to Clock High
ADS
Setup to Clock High
INC
Setup to Clock High
RPT
Setup to Clock High
Hold
Address Hold from Clock High
Chip Enable Hold from Clock High
Byte Enable Hold from Clock High
R/W
Hold from Clock High
Input Data Hold from Clock High
ADS
Hold from Clock High
INC
Hold from Clock High
RPT
Hold from Clock High
Flag
Interrupt Flag Set Time
Interrupt Flag Reset Time
Collision Flag Set Time
Collision Flag Reset Time
Port-to-Port Delay
Clock-to-Clock Delay
t
CYCP
t
CHP
t
CLP
t
CYCF
t
CHF
t
CLF
4
-
-
-
-
-
-
5
2
2
-
-
-
-
-
-
6
-
-
-
-
-
-
7.5
3
3
12
3
3
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
3
3
3
3
3
3
1.7
1.7
6.5
1.7
1.7
2.4
2.4
10
2.4
2.4
7.5
2
2
t
CDP
t
OHP
t
LZCP
t
HZCP
t
CDF
t
OHF
t
LZCF
t
HZCF
t
OE
t
LZOE
t
HZOE
-
1
1
1
-
1
1
1
-
1
1
2.8
-
-
2.8
6.5
-
-
2.8
2.8
-
2.8
-
1
1
1
-
1
1
1
-
1
1
3.4
-
-
3.4
7.5
-
-
3.4
3.4
-
3.4
-
1
1
1
-
1
1
1
-
1
1
3.6
-
-
3.6
10
-
-
3.6
3.6
-
3.6
-
1
1
1
-
1
1
1
-
1
1
4.2
-
-
4.2
12
-
-
4.2
4.2
-
4.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3,8
3,8
3
3,8
3,8
4
4
4
t
AS
t
CES
t
BS
t
WS
t
DS
t
ADSS
t
INCS
t
RPTS
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
-
-
-
-
-
-
-
-
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
-
-
-
-
-
-
-
-
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
-
-
-
-
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
t
AH
t
CEH
t
BH
t
WH
t
DH
t
ADSH
t
INCH
t
RPTH
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
-
-
-
-
-
-
-
-
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
-
-
-
-
-
-
-
-
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
-
-
-
-
-
-
-
-
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
t
SINT
t
RINT
t
SCOL
t
RCOL
-
-
-
-
6
6
-
-
-
-
6
6
-
-
-
-
6
6
-
-
-
-
7
7
ns
ns
ns
ns
2.8
2.8
3.4
3.4
3.6
3.6
4.2
4.2
t
CCO
-
3.5
-
4
-
5
-
ns
7
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| AS9C25512M2018L-166BC | TERM. F/O CABLE ST-SC/ DPLX/RISER/3M/GREEN |
| AS9C25256M2018L-166BC | TERM. F/O CABLE ST-SC/ DPLX/RISER/5M/GREEN |
| AS9C25512M2018L-166BI | TERM. F/O CABLE ST-SC/ DPLX/RISER/10M/GREEN |
| AS9C25256M2018L-166BI | TERM. F/O CABLE ST-SC/ DPLX/RISER/1M/YELLOW |
| AS9C25512M2018L-166FC | TERM. F/O CABLE ST-SC/ DPLX/RISER/2M/YELLOW |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS9C25256M2018L-166BC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25256M2018L-166BI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25256M2018L-166FC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25256M2018L-166FI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
| AS9C25256M2018L-166TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface |
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