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參數(shù)資料
| 型號： | AS91L1002S10L100CG |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The AS91L1006BU is a one to 6-port JTAG gateway |
| 中文描述： | 該AS91L1006BU是一個(gè)6口的JTAG網(wǎng)關(guān) |
| 文件頁數(shù)： | 18/28頁 |
| 文件大小： | 415K |
| 代理商： | AS91L1002S10L100CG |
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July 2004
AS91L1006BU
PIN NAME
PIN
TYPE
PIN
NUMBER
LQFP
63
PIN
NUMBER
FPBGA
F7
DESCRIPTION
Stable state
after port/reset
LSP6_AutoWR
OUT
Flash, Memory Auto-Write on LSP 6
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101;
PRIM_AutoWR is routed to output.
This pin is tri-stated for all other
combinations.
PASS_THRU Debug Enable Output
on LSP 6.
Active low output when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is high for all other
combinations.
IEEE1149.1 Primary Test Clock
Input.
IEEE1149.1 Primary Test Mode
Select Input.
IEEE1149.1 Primary Test Data
Output. This pin is tri-stated when
AS91L1006BUis not selected.
IEEE1149.1 Primary Test Data Input
IEEE1149.1 Primary Test Reset
Input.
This active low asynchronous reset
input signal places AS91L1006U in
Wait-for-Selection state.
Primary Auto-Write Input controlled
by test equipment to shorten Flash
memory programming.
AS91L1006BU Slot Address[5:0]
Inputs.
Used to set address at which
AS91L1006BU will respond; typically
set by hardwired connection on the
backplane.
Test Output Enable Input.
Tri-states all LSPs, when asserted
low.
Logic '1'
LSP6_DE
OUT
65
E10
Logic '1'
PRIM_TCK
IN
87
A6
PRIM_TMS
IN
21
G2
PRIM_TDO
OUT
20
G1
HighZ
PRIM_TDI
PRIM_TRST
IN
IN
19
22
G3
H2
PRIM_AutoWR
IN
16
F1
S[5:0]
IN
8,7,6,5,100,
99
D2,D1,D3,C
2,B2,A2
*TOE
IN
88
B6
www.alsc.com
Alliance Semiconductor
18
2003, 2004 Copyright Alliance Semconductor Corporation. All Rights reserved.
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| AS91L1002S10L100I | Surface Mount Resistors Thick Film Chip Resistors |
| AS91L1002S10L100IG | The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1006S40L100C | The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1006BU10L100IG | Ceramic Conformally Coated / Radial 'Standard & High Voltage Golden Max'; Capacitance [nom]: 3.3pF; Working Voltage (Vdc)[max]: 200V; Capacitance Tolerance: +/-0.5pF; Dielectric: Multilayer Ceramic, Conformally Coated; Temperature Coefficient: C0G (NP0); Lead Style: Radial Leaded; Lead Dimensions: 0.100" Lead Spacing; Body Dimensions: 0.150" x 0.210" x 0.130"; Container: Bag; Qty per Container: 500 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS91L1002S10L100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1002S10L100IF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1002S10L100IG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1002S40F100C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
| AS91L1002S40F100CF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The AS91L1006BU is a one to 6-port JTAG gateway |
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