
AUSTIN SEMICONDUCTOR, INC.
FLASH
AS8F2M32
AS8F2M32
Rev. 2.5 05/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
Austin Semiconductor, Inc.
FIGURE 1: PIN ASSIGNMENT
(Top View)
68 Lead CQFP
2M x 32 FLASH
FLASH MEMORY MODULE
AVAILABLE AS MILITARY
SPECIFICATIONS
Military Processing (MIL-STD-883C para 1.2.2)
Temperature Range -55C to 125C
FEATURES
Fast access times of 90ns, 120ns, and 150ns
5.0V ±10%, single power supply operation
Low power consumption(TYP): 4A CMOS stand-by
* TYP ICC(active) <120mA for READ/WRITE
20 year DATA RETENTION
Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
32 equal sectors of 64 Kbytes each
Any combination of Sectors can be Erased
Group Sector Protection
Supports FULL Chip Erase
Compatible with JEDEC standards
Embedded Erase and Program Algorithms
Data\ Polling and Toggle bits for detection of program or erase
cycle completion.
Erase Suspend/Resume
Hardware Reset pin (RESET\)
Built in Decoupling Caps and Multiple Ground Pins for Low Noise
Operation
Separate Power and Ground Planes to improve noise immunity
OPTION
MARKING
Timing
90ns
-90
120ns
-120
150ns
-150
Packages
Ceramic Quad Flat Pack (0.88" sq)
Q
- MAX height .140"
- Stand-off Height .035" min
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8F2M32 is a 64 Mbit, 5.0 volt-
only Flash memory. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply. The AS8F2M32
offers an access time of 90ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention, the device has
separate chip enable (CE\), write enable (WE\) and output enable (OE\)
controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. internally generated and regulated voltages
are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC
single-power-supply FLASH standard. Commands are written to the
command register using standard microprocessor write timings.
Register contents serve as input to an internal state-matching that
controls the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the programming and
erase operations. Reaching data out of the device is similar to reading
from other FLASH or EPROM devices.
Device programming occurs by executing the program command
sequence. This initiates the Embedded Program algorithm - an internal
algorithm that automatically time the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence.
This initiates the Embedded Erase algorithm - an internal algorithm that
automatically preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies proper cell
margin.
The host system can detect whether a program or erase operation is
complete by observing the RY/BY\ pin, or by reading the DQ7 (DATA\
Polling) and DQ6 (toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array data or accept
another command.
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