參數(shù)資料
型號(hào)： AS80SSTVF16859
廠商： Alliance Semiconductor Corporation
英文描述： DDR 13-Bit to 26-Bit Registered Buffer
中文描述： 復(fù)員13位至26位注冊(cè)緩沖區(qū)
文件頁(yè)數(shù)： 8/13頁(yè)
文件大小： 122K
代理商： AS80SSTVF16859
AS80SSTVF16859
8/6/03, v.0.10
Alliance Semiconductor
P. 8 of 13
Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted.)
Guaranteed by design. Not 100% tested in production
*
This parameter is not necessarily production tested..
Switching Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
(Over recommended operating free-air temperature range unless otherwise noted.)
Switching Characteristics - DDRI-400 (PC3200)
(Over recommended operating free-air temperature range unless otherwise noted.)
Symbol
f
CLOCK
t
W
t
ACT
*
t
INACT
*
Parameters
V
DDQ
= 2.5V±0.2V
Min
V
DDQ
= 2.6V±0.1V
Min
Units
Max
200
22
22
Max
270
22
22
Clock frequency
Pulse duration, CK, CKLB high or low
Differential inputs active time
1
Differential inputs inactive time
2
Setup time, fast slew rate
3,5
Setup time, slow slew rate
4,5
Hold time, fast slew rate
3,5
Hold time, slow slew rate
4,5
MHz
ns
ns
ns
ns
2.5
2.5
1 Data inputs must be low a minimum time of t
ACT
max, after RESETB is taken high
2 Data and clock inputs must be held at valid levels (not floating) a minimum time of t
INACT
max, after RESETB is taken low
3 For data signal input slew rate > 1 V/ns
4 For data signal input slew rte > 0.5 V/ns and < 1 V/ns
5 CLK, CLKB signals iput slew rates are > 1 V/ns
t
S
Data before CLK
↑
,
CLKB
↓
0.75
0.9
0.75
0.9
0.4
0.6
0.4
0.6
ns
ns
t
h
Data after CLK
↑
,
CLKB
↓
ns
Symbol
f
max
From (input)
To (output)
VDD = 2.5 V ± 0.2 V
Min
Typ
200
1.1
1.1
–
Units
MHz
ns
ns
ns
Max
–
2.8
2.8
5.0
–
t
PD
CLK, CLKB (TSSOP)
CLK, CLKB (VFQFN[MLF2])
RESETB
Q
Q
Q
t
phl
–
Symbol
f
max
t
PD
t
PDSS
t
phl
From (input)
To (output)
VDD = 2.6 V ± 0.1 V
Min
Typ
210
1.1
Units
MHz
ns
ns
ns
Max
CLK, CLKB (VFQFN[MLF2])
Simultaneous switching
Q
Q
Q
2.2
2.48
3.5
RESETB
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