參數(shù)資料
型號: AS80M2516A
廠商: Alliance Semiconductor Corporation
英文描述: dual phase lock loop clock chip
中文描述: 雙鎖相環(huán)時(shí)鐘芯片
文件頁數(shù): 8/15頁
文件大小: 439K
代理商: AS80M2516A
November 2003
rev 1.0
AC Timing Specifications (Continued)
Unless otherwise stated, VDD = 3.3.0V ± 10%, no load on any output, and ambient temperature range TA =
0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not
currently produciton tested to any specific limits. MIN and MAX characterization data are ± 3
σ
from typical.
PARAMETER
SYMBOL
CONDITIONS/
DESCRIPTION
Clock Outputs (PLL B clock via FOUT1_CLK2 / FOUT2_CLK2 pins)
Duty Cycle
Ratio of pulse width (as
measured from rising edge to
next falling edge at 2.5V) to one
clock period
On rising edges 500 μs apart at
2.5V relative to an ideal clock,
C
L
= 15pF, f
XIN
=14.318MHz,
F
OUT
= 50MHz , PLL –A
inactive.
On rising edges 500 μs apart at
2.5V relative to an ideal clock,
C
L
= 15pF, f
XIN
=14.318MHz,
F
OUT
= 50MHz, PLL –A active
(60MHz)
From rising edge to the next
rising edge at 2.5V, C
L
= 15pF,
f
XIN
=14.318MHz, F
OUT
= 50MHz
PLL-B inactive.
From rising edge to the next
rising edge at 2.5V, C
L
= 15pF,
f
XIN
=14.318MHz, F
OUT
= 50MHz
PLL-A active (50MHz)
Clock
Stabilization
Time
pin
AS80M2516A
Low Power EMI Reduction IC
8 of 15
Notice: The information in this document is subject to change without notice.
CLOCK
(MHz)
MIN
TYP
MAX
UNIT
100
45
55
%
Jitter, Long
Term (
σ
y(
τ
))*
T
j(LT)
100
45
ps
60
75
Jitter, Period
(peak-peak)
T
j(
P)
100
120
ps
60
400
t
STB
Otput active from power up,
RUN Mode via Power Down
100
ns
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