參數(shù)資料
型號(hào)： AS7C4098-20TCN
廠商： ALLIANCE SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-SOIC -55 to 125
中文描述： 256K X 16 STANDARD SRAM, 20 ns, PDSO44
封裝： LEAD FREE, TSOP2-44
文件頁數(shù)： 7/10頁
文件大?。?/td> 235K
代理商： AS7C4098-20TCN
AS7C4098
AS7C34098
1/13/05;
v.1.9
Alliance Semiconductor
P. 7 of 10
Write waveform 3
10,11
AC test conditions
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11
All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A, B, C.
t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Address
CE
LB, UB
WE
Data
IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
WZ
t
AH
t
WR
Data
OUT
Data undefined
High Z
High Z
t
AS
t
AW
Data valid
10%
90%
10%
90%
GND
+3.0V
2 ns
Figure A: Input pulse
255
C
13
480
D
OUT
GND
+5V
Figure B: 5V Output load
350
C
13
320
D
OUT
GND
+3.3V
Figure C: 3.3V Output load
168
Thevenin equivalent:D
OUT
+1.728V (5V and 3.3V)
相關(guān)PDF資料
PDF描述
AS7C4098-20TI High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-SOIC -55 to 125
AS7C4098-20TIN High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-SOIC -55 to 125
AS7C34098-15JI 5V/3.3V 256K x 16 CMOS SRAM
AS7C34098-15JIN Replaced by SN74LV240A : Octal Buffer/Driver With 3-State Outputs 20-SSOP -40 to 85
AS7C34098-15TC Replaced by SN74LV240A : Octal Buffer/Driver With 3-State Outputs 20-SOIC -40 to 85
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AS7C4098A-12JINTR 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M, 5V, 12ns, FAST 256K x 16 Asyn 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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