參數(shù)資料
型號： AS7C3513-20
廠商： Alliance Semiconductor Corporation
英文描述： Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85
中文描述： 5V/3.3V 32Kx6 CMOS SRAM的
文件頁數(shù)： 6/10頁
文件大?。?/td> 198K
代理商： AS7C3513-20
AS7C513
AS7C3513
3/23/01; v.1.0
Alliance Semiconductor
P. 6 of 10
Data retention characteristics (over the operating range)
13
Parameter
Data retention waveform
AC test conditions
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 2V data retention applies to the commercial operating range only.
14 C=30pF, except on High Z and Low Z parameters, where C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A, B, and C.
These parameters are specified with C
L
= 5pF, as in Figures B or C. Transition is measured
±
500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Symbol
Test conditions
Min
Max
Unit
V
CC
for data retention
Data retention current
V
DR
I
CCDR
t
CDR
t
R
|
I
LI
|
V
CC
= 2.0V
CE
≥
V
CC
–0.2V
V
IN
≥
V
CC
–0.2V
or
V
IN
≤
0.2V
2.0
–
V
μ
A
–
500
Chip deselect to data retention time
0
–
ns
Operation recovery time
t
RC
–
–
ns
μ
A
Input leakage current
1
V
CC
CE
t
R
t
CDR
Data retention mode
V
CC
V
DR
≥
2.0V
V
IH
V
IH
V
DR
V
CC
350
C
(14)
320
D
out
GND
+3.3V
Figure C: 3.3V Output load
168
Thevenin equivalent:
D
out
+1.728V (5V and 3.3V)
255
C
(14)
480
D
out
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
相關(guān)PDF資料
PDF描述
AS7C3513-20JC Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85
AS7C3513-20TC Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85
AS7C3513 Octal Buffers/Drivers With 3-State Outputs 20-SO -40 to 85
AS7C3513-12 Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85
AS7C3513-12JC Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85
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