參數(shù)資料
型號(hào): AS7C34098A-10TC
廠商: ALLIANCE MEMORY INC
元件分類: SRAM
英文描述: 256K X 16 STANDARD SRAM, 10 ns, PDSO44
封裝: TSOP2-44
文件頁(yè)數(shù): 8/10頁(yè)
文件大?。?/td> 262K
代理商: AS7C34098A-10TC
AS7C34098A
8/17/04,v. 2.1
Alliance Memory Inc
P. 7 of 10
Write waveform 3 10
AC test conditions
Notes
1During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2
This parameter is sampled, but not 100% tested.
3
For test conditions, see AC Test Conditions, Figures A and B.
4tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
5
This parameter is guaranteed, but not tested.
6WE is High for read cycle.
7CE and OE are Low for read cycle.
8
Address valid prior to or coincident with CE transition Low.
9
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 All write cycle timings are referenced from the last valid address to the first transitioning address.
11 C=30pF, except on High Z and Low Z parameters, where C=5pF.
Address
CE
LB, UB
WE
DataIN
tWC
tCW
tBW
tWP
tDW
tDH
tWZ
tAH
DataOUT
Data undefined
High Z
tAS
tAW
Data valid
tWR
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
10%
90%
10%
90%
GND
+3.0V
2 ns
Figure A: Input pulse
350
C11
320
DOUT
GND
+3.3V
Figure B: 3.3V Output load
168
DOUT
+1.728V
Thevenin equivalent:
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