參數(shù)資料
型號(hào): AS7C34098
廠商: Alliance Semiconductor Corporation
英文描述: 5V/3.3V 256K x 16 CMOS SRAM
中文描述: 5V/3.3V 256K × 16 CMOS SRAM的
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 235K
代理商: AS7C34098
AS7C4098
AS7C34098
1/13/05;
v.1.9
Alliance Semiconductor
P. 5 of 10
Read waveform 2 (CE, OE, UB, LB controlled)
6,8,9
Write cycle (over the operating range)
11
Parameter
Symbol
–10
–12
–15
–20
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
Chip enable (CE) to write end
t
WC
t
CW
t
AW
t
AS
t
WP1
t
WP2
t
WR
t
AH
t
DW
t
DH
t
WZ
t
OW
t
BW
10
7
12
8
15
10
20
12
ns
ns
Address setup to write end
7
8
10
12
ns
Address setup time
Write pulse width (OE = High)
0
7
0
8
0
0
12
ns
ns
10
Write pulse width (OE = Low)
10
12
15
20
ns
Write recovery time
Address hold from end of write
0
0
0
0
0
0
0
0
ns
ns
Data valid to write end
5
6
7
9
ns
Data hold time
Write enable to output in High-Z
0
0
5
0
0
6
0
0
7
0
0
9
ns
ns
4, 5
4, 5
Output active from write end
3
3
3
3
ns
4, 5
Byte enable Low to write end
7
8
10
12
ns
4, 5
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
CHZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
OUT
相關(guān)PDF資料
PDF描述
AS7C4098-15TI High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-PDIP -55 to 125
AS7C4098-15TIN High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-PDIP -55 to 125
AS7C4098-20 High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-SOIC -55 to 125
AS7C4098-20JC High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-SOIC -55 to 125
AS7C4098-20JCN High Speed CMOS Logic Quad 2-Input Schmitt-Triggered NAND Gates 14-SOIC -55 to 125
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