參數(shù)資料
型號(hào): AS7C34096A-20TCN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: DUAL MONOSTABLE MULTIVIBRATORS 16-TSSOP -40 to 85
中文描述: 512K X 8 STANDARD SRAM, 20 ns, PDSO44
封裝: LEAD FREE, TSOP2-44
文件頁(yè)數(shù): 6/9頁(yè)
文件大?。?/td> 157K
代理商: AS7C34096A-20TCN
AS7C34096A
8/17/04, v. 2.1
Alliance Semiconductor
P. 6 of 9
Write waveform 2 (CE controlled)
10
AC test conditions
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figures A and B.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 All write cycle timings are referenced from the last valid address to the first transitioning address.
11
C=30pF, except on High Z and Low Z parameters, where C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
.
t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
Data valid
t
DH
t
AH
t
WZ
t
WC
t
AS
D
IN
t
WR
350
C
11
320
D
OUT
GND
+3.3V
Figure B: 3.3V Output load
168
Thevenin equivalent:
D
OUT
+1.728V
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
相關(guān)PDF資料
PDF描述
AS7C34096A-20TI DUAL MONOSTABLE MULTIVIBRATORS 16-TSSOP -40 to 85
AS7C34096A-20TIN DUAL MONOSTABLE MULTIVIBRATORS 16-TSSOP -40 to 85
AS7C34096A-10JC 3.3V 512K x 8 CMOS SRAM
AS7C34096A-10JCN 3.3V 512K x 8 CMOS SRAM
AS7C34096A-10JI 3.3V 512K x 8 CMOS SRAM
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