參數(shù)資料
型號(hào): AS7C3364FT32B-75TQCN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 64K x 32/36 Flow Through Synchronous SRAM
中文描述: 64K X 32 STANDARD SRAM, 7.5 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁數(shù): 7/19頁
文件大?。?/td> 417K
代理商: AS7C3364FT32B-75TQCN
AS7C3364FT32B
AS7C3364FT36B
2/8/05; v.1.2
Alliance Semiconductor
P. 7 of 19
Synchronous truth table
[4]
CE0
1
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE
HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ,
OE must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
CE1
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
CE2
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
ADSP
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
ADSC
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
WRITE
[2]
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
OE
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
Address accessed
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
DQ
Hi
Z
Hi
Z
Hi
Z
Hi
Z
Hi
Z
Q
Hi
Z
Q
Hi
Z
Q
Hi
Z
Q
Hi
Z
Q
Hi
Z
Q
Hi
Z
D
3
D
D
D
D
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