- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381344 > AS7C33512PFS18A-166TQC (ALLIANCE SEMICONDUCTOR CORP) 3.3V 512K x 18 pipeline burst synchronous SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | AS7C33512PFS18A-166TQC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| 中文描述： | 512K X 18 STANDARD SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, TQFP-100 |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大小： | 512K |
| 代理商： | AS7C33512PFS18A-166TQC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)
AS7C33512PFS18A
11/30/04;
v.2.2
Alliance Semiconductor
10 of 20
Timing characteristics for 3.3 V I/O operation
Parameter
Symbol
–166
–133
Unit
Notes
1
1
See “Notes” on page 17
Min
Max
Min
Max
Clock frequency
Cycle time
f
Max
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–
6
166
–
–
133
–
MHz
ns
7.5
Clock access time
-
3.5
-
4.0
ns
Output enable low to data valid
–
3.5
–
4.0
ns
Clock high to output low Z
Data output invalid from clock high
0
–
–
0
–
–
ns
ns
2,3,4
2
1.5
1.5
Output enable low to output low Z
0
–
0
–
ns
2,3,4
Output enable high to output high Z
Clock high to output high Z
–
–
3.5
3.5
–
–
4.0
4.0
ns
ns
2,3,4
2,3,4
Output enable high to invalid output
0
–
0
–
ns
Clock high pulse width
Clock low pulse width
2.4
2.3
–
–
2.5
2.5
–
–
ns
ns
5
5
Address setup to clock high
1.5
–
1.5
–
ns
6
Data setup to clock high
Write setup to clock high
1.5
1.5
–
–
1.5
1.5
–
–
ns
ns
6
6,7
Chip select setup to clock high
1.5
–
1.5
–
ns
6,8
Address hold from clock high
Data hold from clock high
0.5
0.5
–
–
0.5
0.5
–
–
ns
ns
6
6
Write hold from clock high
0.5
–
0.5
–
ns
6,7
Chip select hold from clock high
ADV setup to clock high
0.5
1.5
–
–
0.5
1.5
–
–
ns
ns
6,8
6
ADSP setup to clock high
1.5
–
1.5
–
ns
6
ADSC setup to clock high
ADV hold from clock high
1.5
0.5
–
–
1.5
0.5
–
–
ns
ns
6
6
ADSP hold from clock high
0.5
–
0.5
–
ns
6
ADSC hold from clock high
0.5
–
0.5
–
ns
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33512PFS18A-166TQCN | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-166TQI | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-166TQIN | 3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS32A | 3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS36A-133TQI | 3.3V 512K x 32/36 pipelined burst synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33512PFS18A-166TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-166TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-166TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS32A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C33512PFS32A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 32/36 pipelined burst synchronous SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。