參數(shù)資料
型號(hào): AS7C33512NTF36A-10TQCN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 512K x 32/36 Flowthrough Synchronous SRAM with NTD
中文描述: 512K X 36 ZBT SRAM, 10 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁(yè)數(shù): 1/18頁(yè)
文件大?。?/td> 425K
代理商: AS7C33512NTF36A-10TQCN
April 2005
Copyright Alliance Semiconductor. All rights reserved.
AS7C33512NTF32A
AS7C33512NTF36A
4/21/05, v 1.3
Alliance Semiconductor
P. 1 of 18
3.3V 512K × 32/36 Flowthrough Synchronous SRAM with NTD
TM
Features
Organization: 524,288 words × 32 or 36 bits
NTD
architecture for efficient bus operation
Fast clock to data access: 7.5/8.5/10 ns
Fast OE access time:
3.5/4.0 ns
Fully synchronous operation
Flow-through mode
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
Selection guide
-75
8.5
7.5
275
90
60
-85
10
8.5
250
80
60
-10
12
10
230
80
60
Units
ns
ns
mA
mA
mA
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
W
register
Burst logic
D
Q
CLK
Output
Buffer
DQ[a,b,c,d]
19
19
CLK
CEN
CE0
CE1
CE2
A[18:0]
OE
Control
logic
CLK
Data
Input
Register
D
Q
CLK
32/36
32/36
OE
512K x 32/36
SRAM
Array
R/W
BWa
DQ[a,b,c,d]
BWb
BWc
BWd
CLK
Q
D
ADV / LD
LBO
addr. registers
Write delay
19
ZZ
CLK
32/36
32/36
32/36
32/36
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