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參數(shù)資料
| 型號： | AS7C33256PFS18B-166TQC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 256K X 18 pipeline burst synchronous SRAM |
| 中文描述： | 256K X 18 STANDARD SRAM, 8 ns, PQFP100 |
| 封裝： | 14 X 20 MM, TQFP-100 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 536K |
| 代理商： | AS7C33256PFS18B-166TQC |
AS7C33256PFS18B
12/10/04; v.1.7
Alliance Semiconductor
P. 10 of 19
Snooze Mode Electrical Characteristics
Timing characteristics over operating range
Parameter
Sym
–200
–166
–133
Unit
Notes
1
1
See “Notes” on page 16.
Min
Max
Min
–
6
Max
166
–
Min
–
7.5
Max
133
–
Clock frequency
Cycle time
f
Max
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–
200
MHz
ns
5
–
Clock access time
–
3.0
–
3.5
–
4.0
ns
Output enable LOW to data valid
Clock HIGH to output Low Z
–
3.0
–
0
3.5
–
–
0
4.0
–
ns
ns
0
–
2,3,4
Data output invalid from clock HIGH
1.5
–
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
Output enable HIGH to output High Z
0
–
0
–
–
0
–
–
ns
ns
2,3,4
2,3,4
–
3.0
3.5
4.0
Clock HIGH to output High Z
–
3.0
–
3.5
–
4.0
ns
2,3,4
Output enable HIGH to invalid output
Clock HIGH pulse width
0
–
0
–
–
0
–
–
ns
ns
2.0
–
2.4
2.5
5
Clock LOW pulse width
2.3
–
2.4
–
2.5
–
ns
5
Address setup to clock HIGH
Data setup to clock HIGH
1.4
–
1.5
1.5
–
–
1.5
1.5
–
–
ns
ns
6
6
1.4
–
Write setup to clock HIGH
1.4
–
1.5
–
1.5
–
ns
6,7
Chip select setup to clock HIGH
Address hold from clock HIGH
1.4
–
1.5
0.5
–
–
1.5
0.5
–
–
ns
ns
6,8
6
0.4
–
Data hold from clock HIGH
0.4
–
0.5
–
0.5
–
ns
6
Write hold from clock HIGH
Chip select hold from clock HIGH
0.4
–
0.5
0.5
–
–
0.5
0.5
–
–
ns
ns
6,7
6,8
0.4
–
ADV setup to clock HIGH
1.4
–
1.5
–
1.5
–
ns
6
ADSP setup to clock HIGH
1.4
–
1.5
–
1.5
–
ns
6
ADSC setup to clock HIGH
ADV hold from clock HIGH
1.4
–
1.5
0.5
–
–
1.5
0.5
–
–
ns
ns
6
6
0.4
–
ADSP hold from clock HIGH
0.4
–
0.5
–
0.5
–
ns
6
ADSC hold from clock HIGH
0.4
–
0.5
–
0.5
–
ns
6
Description
Conditions
ZZ > V
IH
Symbol
I
SB2
t
PDS
t
PUS
t
ZZI
t
RZZI
Min
Max
30
Units
mA
cycle
cycle
cycle
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2
2
2
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33256PFS18B-166TQCN | 3.3V 256K X 18 pipeline burst synchronous SRAM |
| AS7C33256PFS18B-166TQI | 3.3V 256K X 18 pipeline burst synchronous SRAM |
| AS7C33256PFS18B-166TQIN | 3.3V 256K X 18 pipeline burst synchronous SRAM |
| AS7C33256PFS18B-200TQC | 3.3V 256K X 18 pipeline burst synchronous SRAM |
| AS7C33256PFS18B-200TQCN | 3.3V 256K X 18 pipeline burst synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33256PFS18B-166TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 18 pipeline burst synchronous SRAM |
| AS7C33256PFS18B-166TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 18 pipeline burst synchronous SRAM |
| AS7C33256PFS18B-166TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 18 pipeline burst synchronous SRAM |
| AS7C33256PFS18B-200TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 18 pipeline burst synchronous SRAM |
| AS7C33256PFS18B-200TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K X 18 pipeline burst synchronous SRAM |
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