- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄381340 > AS7C33256PFD36A-133TQC (ALLIANCE SEMICONDUCTOR CORP) 3.3V 256K x 32/36 pipelined burst synchronous SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | AS7C33256PFD36A-133TQC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| 中文描述： | 256K X 36 STANDARD SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, TQFP-100 |
| 文件頁(yè)數(shù)： | 1/20頁(yè) |
| 文件大?。?/td> | 527K |
| 代理商： | AS7C33256PFD36A-133TQC |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)
December 2004
AS7C33256PFD32A
AS7C33256PFD36A
3.3V 256K
×
32/36 pipelined burst synchronous SRAM
12/1/04, v.1.2
Alliance Semiconductor
P. 1 of 20
Copyright Alliance Semiconductor. All rights reserved.
Features
Organization: 262,144 words x 32 or 36 bits
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/4.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous register-to-register operation
Dual-cycle deselect
Asynchronous output enable control
Available in100-pin TQFP
Logic block diagram
Q0
Q1
18
256K × 32/36
Memory
array
Burst logic
CLK
CE
CLR
Address
register
D
CE
CLK
Q
DQ
CLK
D
Q
Byte write
registers
DQ
CLK
D
Q
registers
DQ
CLK
D
Q
Byte write
registers
DQ
CLK
D
Q
Byte write
registers
Enable
register
CLK
D
Q
Enable
rdelay
CLK
D
Q
CE
Output
registers
CLK
Input
registers
CLK
Power
down
4
36/32
18
16
18
GWE
d
BWE
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BW
c
BW
b
BW
a
OE
A
[17:0]
ZZ
LBO
OE
36/32
36/32
DQ[a:d]
2
2
Selection guide
–166
–133
Units
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
7.5
133
4
425
100
30
ns
166
3.5
475
130
30
MHz
ns
mA
mA
mA
Individual byte write and global write
Multiple chip enables for easy expansion
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33256PFD36A-133TQCN | 3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFD36A-133TQI | 3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFD36A-133TQIN | 3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFS18A | 3.3V 256K×18 Ppipeline Burst Synchronous SRAM(3.3V 256K×18流水線脈沖同步靜態(tài)RAM) |
| AS7C33256PFS18B | 3.3V 256K X 18 pipeline burst synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33256PFD36A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFD36A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFD36A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFD36A-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| AS7C33256PFD36A-166TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 32/36 pipelined burst synchronous SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。