參數(shù)資料
型號: AS7C33256NTD36A-166TQI
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD
中文描述: 256K X 36 ZBT SRAM, 3.8 ns, PQFP100
封裝: 14 X 20 MM, TQFP-100
文件頁數(shù): 5/19頁
文件大?。?/td> 441K
代理商: AS7C33256NTD36A-166TQI
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 5 of 19
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The
duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs
except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed
to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations
are completed. Similarly, when exiting SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while
the SRAM is transitioning out of SNOOZE MODE.
Signal descriptions
Signal
I/O
Properties Description
CLK
CEN
I
I
CLOCK
SYNC
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
A, A0, A1
I
SYNC
Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b,c,d]
CE0, CE1,
CE2
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
I
SYNC
ADV/LD
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
R/W
I
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
BW[a,b,c,d]
I
SYNC
OE
I
ASYNC
Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO
I
STATIC
Selects Burst mode. When tied to V
DD
or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order.
This signal is internally pulled
High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
ZZ
I
ASYNC
NC
-
-
No connect. Note that pin 84 will be used for future address expansion to 16Mb density.
相關(guān)PDF資料
PDF描述
AS7C33256NTD36A-166TQIN 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD
AS7C33256NTD32A 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD
AS7C33256NTD32A-133TQC 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD
AS7C33256NTD32A-133TQCN 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD
AS7C33256NTD32A-133TQI 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS7C33256NTD36A-166TQIN 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD
AS7C33256NTF18B 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 18 Flowthrough Synchronous SRAM with NTD
AS7C33256NTF18B-10TQC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 18 Flowthrough Synchronous SRAM with NTD
AS7C33256NTF18B-10TQCN 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 18 Flowthrough Synchronous SRAM with NTD
AS7C33256NTF18B-10TQI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 256K x 18 Flowthrough Synchronous SRAM with NTD