- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄382860 > AS7C33128PFD18B-166TQCN (ALLIANCE SEMICONDUCTOR CORP) 3.3V 128K x 18 pipeline burst synchronous SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | AS7C33128PFD18B-166TQCN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 3.3V 128K x 18 pipeline burst synchronous SRAM |
| 中文描述： | 128K X 18 STANDARD SRAM, 3.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁(yè)數(shù)： | 10/19頁(yè) |
| 文件大?。?/td> | 538K |
| 代理商： | AS7C33128PFD18B-166TQCN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
AS7C33128PFD18B
1/31/05; v.1.2
Alliance Semiconductor
P. 10 of 19
Snooze Mode Electrical Characteristics
Timing characteristics over operating range
Parameter
Sym
–200
–166
–133
Unit
Notes
1
1
See “Notes” on page 16.
Min
Max
Min
–
Max
166
Min
–
Max
133
Clock frequency
f
Max
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–
200
MHz
Cycle time
Clock access time
5
–
6
–
–
7.5
–
–
ns
ns
–
3.0
3.5
4.0
Output enable LOW to data valid
–
3.0
–
3.5
–
4.0
ns
Clock HIGH to output Low Z
0
–
0
–
0
–
ns
2,3,4
Data output invalid from clock HIGH
Output enable LOW to output Low Z
1.5
–
1.5
0
–
–
1.5
0
–
–
ns
ns
2
0
–
2,3,4
Output enable HIGH to output High Z
–
3.0
–
3.5
–
4.0
ns
2,3,4
Clock HIGH to output High Z
Output enable HIGH to invalid output
–
3.0
–
0
3.5
–
–
0
4.0
–
ns
ns
2,3,4
0
–
Clock HIGH pulse width
2.0
–
2.4
–
2.5
–
ns
5
Clock LOW pulse width
Address setup to clock HIGH
2.3
–
2.4
1.5
–
–
2.5
1.5
–
–
ns
ns
5
6
1.4
–
Data setup to clock HIGH
1.4
–
1.5
–
1.5
–
ns
6
Write setup to clock HIGH
Chip select setup to clock HIGH
1.4
–
1.5
1.5
–
–
1.5
1.5
–
–
ns
ns
6,7
6,8
1.4
–
Address hold from clock HIGH
0.4
–
0.5
–
0.5
–
ns
6
Data hold from clock HIGH
Write hold from clock HIGH
0.4
–
0.5
0.5
–
–
0.5
0.5
–
–
ns
ns
6
0.4
–
6,7
Chip select hold from clock HIGH
0.4
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock HIGH
ADSP setup to clock HIGH
1.4
–
1.5
1.5
–
–
1.5
1.5
–
–
ns
ns
6
6
1.4
–
ADSC setup to clock HIGH
1.4
–
1.5
–
1.5
–
ns
6
ADV hold from clock HIGH
ADSP hold from clock HIGH
0.4
–
0.5
0.5
–
–
0.5
0.5
–
–
ns
ns
6
6
0.4
–
ADSC hold from clock HIGH
0.4
–
0.5
–
0.5
–
ns
6
Description
Conditions
ZZ > V
IH
Symbol
I
SB2
t
PDS
t
PUS
t
ZZI
t
RZZI
Min
Max
30
Units
mA
cycle
cycle
cycle
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2
2
2
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33128PFD18B-166TQI | 3.3V 128K x 18 pipeline burst synchronous SRAM |
| AS7C33128PFD18B-166TQIN | 3.3V 128K x 18 pipeline burst synchronous SRAM |
| AS7C33128PFD18B-200TQC | 3.3V 128K x 18 pipeline burst synchronous SRAM |
| AS7C33128PFD18B-200TQCN | 3.3V 128K x 18 pipeline burst synchronous SRAM |
| AS7C33128PFD18B-200TQI | 3.3V 128K x 18 pipeline burst synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33128PFD18B-166TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 18 pipeline burst synchronous SRAM |
| AS7C33128PFD18B-166TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 18 pipeline burst synchronous SRAM |
| AS7C33128PFD18B-200TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 18 pipeline burst synchronous SRAM |
| AS7C33128PFD18B-200TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 18 pipeline burst synchronous SRAM |
| AS7C33128PFD18B-200TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128K x 18 pipeline burst synchronous SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。