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參數(shù)資料
| 型號(hào)： | AS7C33128NTD18B |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 3.3V 128Kx18 Pipelined SRAM with NTD |
| 中文描述： | 3.3 128Kx18與新臺(tái)幣流水線的SRAM |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 443K |
| 代理商： | AS7C33128NTD18B |
AS7C33128NTD18B
4/28/05
;
v.1.3
Alliance Semiconductor
P. 5 of 19
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
Burst order
Signal descriptions
Signal
I/O
Properties
Description
CLK
CEN
I
CLOCK
Clock. All inputs except
OE
,
LBO
, and ZZ are synchronous to this clock.
I
I
SYNC
SYNC
Clock enable. When de-asserted HIGH, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/
LD
is asserted.
A, A0, A1
DQ[a,b]
CE0
, CE1,
CE2
I/O
SYNC
Data. Driven as output when the chip is enabled and
OE
is active.
I
SYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/
LD
is asserted.
Are ignored when ADV/
LD
is HIGH.
Advance or Load. When sampled HIGH, the internal burst address counter will increment
in the order defined by the
LBO
input value. When LOW, a new address is loaded.
ADV/
LD
I
SYNC
R/
W
I
SYNC
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a
WRITE operation. Is ignored when ADV/
LD
is HIGH.
BW[a,b]
I
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when
OE
is inactive.
OE
I
ASYNC
LBO
I
STATIC
Selects Burst mode. When tied to V
DD
or left floating, device follows interleaved Burst
order. When driven Low, device follows linear Burst order.
This signal is internally pulled
High.
ZZ
NC
I
-
ASYNC
-
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects.
Interleaved burst order (LBO = 1)
A1 A0
Starting address
0 0
First increment
0 1
Second increment
1 0
Third increment
1 1
Linear burst order (LBO = 0)
A1 A0
Starting Address
First increment
Second increment
Third increment
A1 A0
0 1
0 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
1 0
0 1
0 0
A1 A0
0 1
1 0
1 1
0 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
0 0
0 1
1 0
0 0
0 1
1 0
1 1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C33128NTD18B-133TQC | 3.3V 128Kx18 Pipelined SRAM with NTD |
| AS7C33128NTD18B-133TQCN | 3.3V 128Kx18 Pipelined SRAM with NTD |
| AS7C33128NTD18B-133TQI | 3.3V 128Kx18 Pipelined SRAM with NTD |
| AS7C33128NTD18B-133TQIN | 3.3V 128Kx18 Pipelined SRAM with NTD |
| AS7C33128NTD18B-166TQC | 3.3V 128Kx18 Pipelined SRAM with NTD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C33128NTD18B-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx18 Pipelined SRAM with NTD |
| AS7C33128NTD18B-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx18 Pipelined SRAM with NTD |
| AS7C33128NTD18B-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx18 Pipelined SRAM with NTD |
| AS7C33128NTD18B-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx18 Pipelined SRAM with NTD |
| AS7C33128NTD18B-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128Kx18 Pipelined SRAM with NTD |
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