參數(shù)資料
型號(hào): AS7C31026B-12TIN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 8-Bit Parallel-Load Shift Registers 16-TSSOP -40 to 85
中文描述: 64K X 16 STANDARD SRAM, 12 ns, PDSO44
封裝: 10.20 X 18.40 MM, LEAD FREE, TSOP2-44
文件頁數(shù): 7/10頁
文件大小: 122K
代理商: AS7C31026B-12TIN
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 7 of 10
AC test conditions
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5
Notes
1
2
3
4
5
6
7
8
9
10 N/A
11
12 Not applicable.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A and B.
These parameters are specified with C
L
= 5 pF, as in Figures B. Transition is measured ± 500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
255
C
13
320
GND
+3.3 V
Figure B: 3.3 V Output load
168
Thevenin Equivalent:
D
OUT
+1.728 V
10%
90%
10%
90%
GND
+3.0 V
Figure A: Input pulse
2 ns
D
OUT
相關(guān)PDF資料
PDF描述
AS7C31026B-15JC 8-Bit Parallel-Load Shift Registers 16-TSSOP -40 to 85
AS7C31026B-15JCN 8-Bit Parallel-Load Shift Registers 16-TSSOP -40 to 85
AS7C31026B-15JI 8-Bit Parallel-Load Shift Registers 16-TSSOP -40 to 85
AS7C31026B-15JIN 8-Bit Parallel-Load Shift Registers 16-TSSOP -40 to 85
AS7C31026B-15TC Replaced by SN74LV174A : Hex D-Type Flip-Flop With Clear 16-SOIC -40 to 85
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