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參數(shù)資料
| 型號(hào)： | AS7C31026B-12TCN |
| 廠商： | ALLIANCE MEMORY INC |
| 元件分類： | SRAM |
| 英文描述： | IC,AS7C31026B-12TCN,TSOP-32 I, SRAM,12NS,64K X 16,3.3V |
| 中文描述： | 64K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | 10.20 X 18.40 MM, LEAD FREE, TSOP2-44 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 122K |
| 代理商： | AS7C31026B-12TCN |
AS7C31026B
3/26/04, v 1.3
Alliance Semiconductor
P. 2 of 10
Functional description
The AS7C31026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words
× 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for
high-performance applications.
When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The device is packaged in common industry
standard packages.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key: H = high, L = low, X = don’t care.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.50
+5.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–1.0
W
Storage temperature (plastic)
Tstg
–65
+150
°C
Ambient temperature with VCC applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–20
mA
Truth table
CE
WE
OE
LB
UB
I/O0–I/O7
I/O8–I/O15
Mode
H
X
High Z
Standby (ISB), ISBI)
LH
L
H
DOUT
High Z
Read I/O0–I/O7 (ICC)
L
H
L
H
L
High Z
DOUT
Read I/O8–I/O15 (ICC)
L
H
LLL
DOUT
Read I/O0–I/O15 (ICC)
LL
X
L
DIN
Write I/O0–I/O15 (ICC)
LL
X
L
H
DIN
High Z
Write I/O0–I/O7 (ICC)
L
X
H
L
High Z
DIN
Write I/O8–I/O15 (ICC)
L
H
X
H
X
H
X
H
High Z
Output disable (ICC)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C31026B-12TCNTR | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1M, 3.3V, 12ns, FAST 64K x 16 Asynch 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| AS7C31026B-12TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V 64K X 16 CMOS SRAM |
| AS7C31026B-12TIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V 64K X 16 CMOS SRAM |
| AS7C31026B-12TJCN | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 Fast Asynch 3.3V 64Kx16 12ns 1Mb RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| AS7C31026B-15JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3 V 64K X 16 CMOS SRAM |
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