- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄381327 > AS7C31026-20 (Alliance Semiconductor Corporation) 5V/3.3V 64Kx6 CMOS SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | AS7C31026-20 |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5V/3.3V 64Kx6 CMOS SRAM |
| 中文描述： | 5V/3.3V 64Kx6 CMOS SRAM的 |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 239K |
| 代理商： | AS7C31026-20 |
S
2
ALLIANCE SEMICONDUCTOR
DID 11-20011-A. 5/22/00
AS7C1026
AS7C31026
Functional description
The AS7C1026 and AS7C31026 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 65,536 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5/6/8/10 ns
are ideal for high-performance applications.
When CE is high the devices enter stanby mode. The AS7C1026 is guaranteed not to exceed 28 mW power consumption in
CMOS standby mode. The devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026) or 3.3V supply
(AS7C31026). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in
manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and
external dimensions of 8 mm × 6 mm.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
L
L
Parameter
Symbol
V
t1
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–0.50
–
–65
–55
–
Max
+7.0
+5.0
Unit
V
V
V
W
°
C
°
C
mA
Voltage on V
CC
relative to GND
AS7C1026
AS7C31026
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
V
CC
+0.50
1.0
+150
+125
20
WE
X
H
H
H
L
L
OE
X
L
L
L
X
X
LB
X
L
H
L
L
L
UB
X
H
L
L
L
H
I/O0–I/O7
High Z
D
OUT
High Z
D
OUT
D
IN
D
IN
I/O8–I/O15
High Z
High Z
D
OUT
D
OUT
D
IN
High Z
Mode
Standby (I
SB
), I
SBI
)
Read I/O0–I/O7 (I
CC
)
Read I/O8–I/O15 (I
CC)
Read I/O0–I/O15 (I
CC
)
Write I/O0–I/O15 (I
CC
)
Write I/O0–I/O7 (I
CC
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1026-20BC | 5V/3.3V 64Kx6 CMOS SRAM |
| AS7C1026-20TC | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 |
| AS7C31026-20JC | 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85 |
| AS7C31026-20TC | 8-Bit Parallel-Load Shift Registers 16-TSSOP -40 to 85 |
| AS7C31026-20TI | 8-Bit Parallel-Load Shift Registers 16-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C31026-20BC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V / 3.3V 64KX16 CMOS SRAM |
| AS7C31026-20BI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V / 3.3V 64KX16 CMOS SRAM |
| AS7C31026-20JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 64Kx6 CMOS SRAM |
| AS7C31026-20JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V / 3.3V 64KX16 CMOS SRAM |
| AS7C31026-20TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V / 3.3V 64KX16 CMOS SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。