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參數(shù)資料
| 型號(hào)： | AS7C31025A-20TC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | Parallel-Load 8-Bit Shift Registers 16-VQFN -40 to 85 |
| 中文描述： | 128K X 8 STANDARD SRAM, 20 ns, PDSO32 |
| 封裝： | TSOP2-32 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 116K |
| 代理商： | AS7C31025A-20TC |
January 2001
Advance Information
Copyright Alliance Semiconductor. All rights reserved.
AS7C1025A
AS7C31025A
5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout)
2/6/01; V0.9
Alliance Semiconductor
P. 1 of 8
Features
AS7C1025A (5V version)
AS7C31025A (3.3V version)
Industrial and commercial temperatures
Organization: 131,072 x 8 bits
High speed
- 10/10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
Low power consumption: ACTIVE
- 660 mW (AS7C1025A) / max @ 10 ns (5V)
- 324 mW (AS7C31025A) / max @ 10 ns (3.3V)
Low power consumption: STANDBY
- 55 mW (AS7C1025A) / max CMOS (5V)
- 36 mW (AS7C31025A) / max CMOS (3.3V)
Latest 6T 0.25u CMOS technology
2.0V data retention
Easy memory expansion with
CE
,
OE
inputs
Center power and ground
TTL/LVTTL-compatible, three-state I/O
JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin, TSOP II
ESD protection
≥
2000 volts
Latch-up current
≥
200 mA
Pin arrangement
Logic block diagram
512
×
256
×
8
Array
(1,048,576)
S
Input buffer
A
A
A
A
A
A
A
I/O0
I/O7
OE
CE
WE
Column decoder
R
Control
circuit
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A
A
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
V
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
I/O5
I/O4
A12
A11
A10
A9
A8
32-pin TSOP II
A
A
Selection guide
AS7C1025A-10
AS7C31025A-10
AS7C1025A-12
AS7C31025A-12
AS7C1025A-15
AS7C31025A-15
AS7C1025A-20
AS7C31025A-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access
time
3
3
4
5
ns
Maximum
operating
current
AS7C1025A
120
110
100
100
mA
AS7C31025A
90
80
80
80
mA
Maximum
CMOS standby
current
AS7C1025A
10
10
10
15
mA
AS7C31025A
10
10
10
15
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C31025A-20TI | Parallel-Load 8-Bit Shift Registers 16-VQFN -40 to 85 |
| AS7C31025A-20TJI | 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025B-10JC | 5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-10JCN | 5V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C1025B-10JI | 5V 128K X 8 CMOS SRAM (Center power and ground) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C31025A-20TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025A-20TJC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025A-20TJI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025B | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 8 CMOS SRAM (Center power and ground) |
| AS7C31025B-10JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 128K X 8 CMOS SRAM (Center power and ground) |
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