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參數(shù)資料
| 型號(hào)： | AS7C31025-20JI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout) |
| 中文描述： | 128K X 8 STANDARD SRAM, 20 ns, PDSO32 |
| 封裝： | 0.400 INCH, SOJ-32 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 196K |
| 代理商： | AS7C31025-20JI |
March 2001
AS7C1025
AS7C31025
5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout)
Copyright Alliance Semiconductor. All rights reserved.
3/23/01; v.1.0
Alliance Semiconductor
P. 1 of 9
Features
AS7C1025 (5V version)
AS7C31025 (3.3V version)
Industrial and commercial temperatures
Organization: 131,072 words × 8 bits
High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
Low power consumption: ACTIVE
- 715 mW (AS7C1025) / max @ 12 ns (5V)
- 360 mW (AS7C31025) / max @ 12 ns (3.3V)
Low power consumption: STANDBY
- 27.5 mW (AS7C1025) / max CMOS (5V)
- 1.8 mW (AS7C31025) / max CMOS (3.3V)
2.0V data retention
Easy memory expansion with CE, OE inputs
Center power and ground
TTL/LVTTL-compatible, three-state I/O
JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin TSOP II
ESD protection
≥
2000 volts
Latch-up current
≥
200 mA
Logic block diagram
512
×
256
×
8
Array
(1,048,576)
S
Input buffer
A
A
A
A
A
A
A
I/O0
I/O7
OE
CE
WE
Column decoder
R
Control
circuit
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
GND
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A
A
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
V
I/O5
I/O4
A12
A11
A10
A9
A8
32-pin TSOP II
A
A
Selection guide
Shaded areas contain advance information.
AS7C1025-12
AS7C31025-12
AS7C1025-15
AS7C31025-15
AS7C1025-20
AS7C31025-20
Unit
Maximum address access time
12
15
20
ns
Maximum output enable access time
3
4
5
ns
Maximum operating current
AS7C1025
130
85
80
mA
AS7C31025
100
85
80
mA
Maximum CMOS standby current
AS7C1025
5
5
5
mA
AS7C31025
5
5
5
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1025 | High Speed CMOS Logic Quad 2-Input AND Gates 14-PDIP -55 to 125 |
| AS7C1025-20TC | 5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025-20TI | High Speed CMOS Logic Quad 2-Input AND Gates 14-SOIC -55 to 125 |
| AS7C1025-20TJI | High Speed CMOS Logic Quad 2-Input AND Gates 14-SOIC -55 to 125 |
| AS7C31025 | Parallel-Load 8-Bit Shift Registers 16-SSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C31025-20TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025-20TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025-20TJC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025-20TJI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5V/3.3V 128K x 8 CMOS SRAM (Revolutionary pinout) |
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