參數(shù)資料
型號(hào): AS7C31024B-20TJC
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 128 x 64 pixel format, LED or EL Backlight available
中文描述: 128K X 8 STANDARD SRAM, 20 ns, PDSO32
封裝: 0.300 INCH, PLASTIC, SOJ-32
文件頁(yè)數(shù): 6/9頁(yè)
文件大?。?/td> 120K
代理商: AS7C31024B-20TJC
AS7C31024B
3/24/04, v.1.2
Alliance Semiconductor
P. 6 of 9
Write waveform 2 (CE1 and CE2 controlled)
10,11,12
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 N/A
11
12 CE1 and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
14 N/A
During V
CC
power-up, a pull-up resistor to V
CC
on CE1 is required to meet I
SB
specification.
This parameter is sampled and not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A, and B.
t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is high for read cycle.
CE1 and OE are low and CE2 is high for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
t
AW
Address
CE1
WE
D
OUT
t
CW1
, t
CW2
t
WP
t
DW
Data valid
t
DH
t
AH
t
WR
t
WC
t
AS
CE2
D
IN
t
WZ
255
– Output load: see Figure B.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
C
13
320
D
OUT
GND
+3.3V
168
Thevenin equivalent:
D
OUT
+1.728V
Figure B: 3.3V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
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