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參數(shù)資料
| 型號： | AS7C31024A-12TJC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Bit Synchronous Binary Counters 16-TSSOP -40 to 85 |
| 中文描述： | 128K X 8 STANDARD SRAM, 12 ns, PDSO32 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 116K |
| 代理商： | AS7C31024A-12TJC |
May 2002
Copyright Alliance Semiconductor. All rights reserved.
AS7C1024A
AS7C31024A
5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)
9/26/02; 0.9.9
Alliance Semiconductor
P. 1 of 9
Features
AS7C1024A (5V version)
AS7C31024A (3.3V version)
Industrial and commercial temperatures
Organization: 131,072 words x 8 bits
High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
Low power consumption: ACTIVE
- 853 mW (AS7C1024A) / max @ 10 ns
- 522 mW (AS7C31024A) / max @ 10 ns
Low power consumption: STANDBY
- 55 mW (AS7C1024A) / max CMOS
- 36 mW (AS7C31024A) / max CMOS
Latest 6T 0.25u CMOS technology
Easy memory expansion with CE1, CE2, OE inputs
TTL/LVTTL-compatible, three-state I/O
32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
ESD protection
≥
2000 volts
Latch-up current
≥
200 mA
Pin arrangement
Logic block diagram
512
×
256
×
8
Array
(1,048,576)
S
Input buffer
A
A
A
A
A
A
A
I/O0
I/O7
CE1
CE2
OE
Column decoder
R
Control
circuit
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A
A
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
V
CC
NC
A14
A12
A7
A6
A5
A4
A15
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A3
A2
A1
A0
I/O0
I/O2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
32-pin (8 x 20mm) TSOP I
32-pin (8 x 13.4mm) sTSOP1
Selection guide
-10
10
5
155
145
10
5
-12
12
6
150
140
10
5
-15
15
7
145
135
10
5
-20
20
8
140
130
10
5
Unit
ns
ns
mA
mA
mA
mA
Maximum address access time
Maximum output enable access time
Maximum
operating current
AS7C1024A
AS7C31024A
AS7C1024A
AS7C31024A
Maximum CMOS
standby current
相關PDF資料 |
PDF描述 |
|---|---|
| AS7C31024A-12TJI | 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-15JC | 4-Bit Synchronous Binary Counters 16-TSSOP -40 to 85 |
| AS7C31024A-15JI | 4-Bit Synchronous Binary Counters 16-TSSOP -40 to 85 |
| AS7C31024A-15STC | 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-15STI | 4-Bit Synchronous Binary Counters 16-TSSOP -40 to 85 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C31024A-12TJI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-15JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-15JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-15STC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-15STI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
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