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參數(shù)資料
| 型號： | AS7C31024A-10TJI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| 中文描述： | 128K X 8 STANDARD SRAM, 10 ns, PDSO32 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 116K |
| 代理商： | AS7C31024A-10TJI |
AS7C1024A
AS7C31024A
9/26/02; 0.9.9
Alliance Semiconductor
P. 6 of 9
AC test conditions
– Output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C=30pF, except all high Z and low Z parameters, C=5pF.
14 2V data retention applies to commercial temperature operating range only.
During V
CC
power-up, a pull-up resistor to V
CC
on CE1 is required to meet I
SB
specification.
This parameter is sampled and not 100% tested.
For test conditions, see
AC Test Condtions
, Figures A, B, and C.
t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE1 and OE are Low and CE2 is High for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
255
C(14)
320
D
OUT
GND
+3.3V
168
Thevenin equivalent:
D
OUT
+1.728V (5V and 3.3V)
Figure C: 3.3V Output load
255
C(14)
480
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
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| AS7C1024A-12JC | 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10JC | 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10JI | 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10STC | 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-10STI | 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C31024A-12JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-12JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-12STC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-12STI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024A-12TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout) |
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