參數(shù)資料
型號: AS7C31024-20TC
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
中文描述: 128K X 8 STANDARD SRAM, 20 ns, PDSO32
封裝: 8 X 20 MM, TSOP1-32
文件頁數(shù): 4/9頁
文件大?。?/td> 208K
代理商: AS7C31024-20TC
4
ALLIANCE SEMICONDUCTOR
11/29/00
AS7C1024
AS7C31024
Read cycle (over the operating range)
3,9,12
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9,12
Read waveform 2 (CE1, CE2, and OE controlled)
3,6,8,9,12
Parameter
Symbol
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
t
CLZ1
t
CLZ2
t
CHZ1
t
CHZ2
t
OLZ
t
OHZ
t
PU
t
PD
-10
-12
-15
-20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
10
2
3
3
0
0
Max
10
10
10
3
3
3
3
10
Min
12
3
3
3
0
0
Max
12
12
12
3
3
3
3
12
Min
15
3
3
3
0
0
Max
15
15
15
4
4
4
4
15
Min
20
3
3
3
0
0
Max
20
20
20
5
5
5
5
20
Read cycle time
Address access time
Chip enable (CE1) access time
Chip enable (CE2) access time
Output enable (OE) access time
Output hold from address change
CE1 Low to output in low Z
CE2 High to output in low Z
CE1 Low to output in high Z
CE2 Low to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
Power down time
3
3, 12
3, 12
5
4, 5, 12
4, 5, 12
4, 5, 12
4, 5, 12
4, 5
4, 5
4, 5, 12
4, 5, 12
Undefined / don’t care
Falling input
Rising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
supply
Current
CE2
OE
D
OUT
t
OE
t
OLZ
t
ACE1
,
tACE2
t
CHZ1
, t
CHZ2
t
CLZ1
, t
CLZ2
t
PU
t
PD
I
CC
I
SB
50%
50%
Data valid
t
RC1
CE1
t
OHZ
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS7C31024-20TI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-20TJC 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-20TJI 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-20TPC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM
AS7C31024-25JC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM