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參數(shù)資料
| 型號(hào)： | AS7C25512PFS36A-166TQIN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2.5V 512K x 32/36 pipelined burst synchronous SRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 3.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁(yè)數(shù)： | 6/19頁(yè) |
| 文件大?。?/td> | 522K |
| 代理商： | AS7C25512PFS36A-166TQIN |
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AS7C25512PFS32A
AS7C25512PFS36A
12/23/04, v. 2.2
Alliance Semiconductor
6 of 19
Write enable truth table (per byte)
Key:
X = don’t care, L = low, H = high, n = a, b, c, d;
BWE
,
BWn
= internal write signal.
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Function
GWE
BWE
BWa
BWb
BWc
BWd
Write All Bytes
L
X
X
X
X
X
H
L
L
L
L
L
Write Byte a
H
L
L
H
H
H
Write Byte c and d
H
L
H
H
L
L
Read
H
H
X
X
X
X
H
L
H
H
H
H
Operation
ZZ
H
L
L
L
L
OE
X
L
H
X
X
I/O Status
High-Z
Dout
High-Z
Din, High-Z
High-Z
Snooze mode
Read
Write
Deselected
Interleaved burst address (LBO = 1)
A1 A0
Starting Address
First Increment
Second Increment
Third Increment
Linear burst address (LBO = 0)
A1 A0
Starting Address
First Increment
Second Increment
Third Increment
A1 A0
0 1
0 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
1 0
0 1
0 0
A1 A0
0 1
1 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 1
0 0
0 1
1 0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
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