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參數(shù)資料
| 型號： | AS7C25512PFD36A-133TQCN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2.5V 512K x 32/36 pipelined burst synchronous SRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 3.8 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 523K |
| 代理商： | AS7C25512PFD36A-133TQCN |
2/10/05, v. 1.2
Alliance Semiconductor
11 of 19
AS7C25512PFD32A
AS7C25512PFD36A
Key to switching waveforms
Timing waveform of read cycle
Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. BW[a:d] is don’t care.
*Outputs are disabled within two clk cycles after DSEL command
don’t care
Falling input
Rising input
Undefined
CE1
t
CYC
t
CL
t
CH
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
Dout
t
CSS
t
HZC
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
LOAD NEW ADDRESS
ADV inserts wait states
Q(A2Y10)
Q(A2Y11)
Q(A3)
Q(A2)
Q(A2Y01)
Q(A3Y01)
Q(A3Y10)
Q(A1)
A2
A1
A3
t
OE
t
LZOE
t
CSH
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Burst
Read
Q(A2Y01)
Read
Q(A3)
DSEL*
Burst
Read
Q(A2Y10)
Suspend
Read
Q(A2Y10)
Burst
Read
Q(A2Y11)
Burst
Read
Q(A3Y01)
Burst
Read
Q(A3Y10)
Burst
Read
Q(A3Y11)
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