參數(shù)資料
型號(hào): AS7C25512NTD36A-166TQI
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 2.5V 512K x 32/36 Pipelined SRAM with NTD
中文描述: 512K X 36 ZBT SRAM, 3.5 ns, PQFP100
封裝: 14 X 20 MM, TQFP-100
文件頁(yè)數(shù): 9/18頁(yè)
文件大?。?/td> 428K
代理商: AS7C25512NTD36A-166TQI
AS7C25512NTD32A/36A
12/23/04, v 2.2
Alliance Semiconductor
P. 9 of 18
Timing characteristics over operating range
Snooze Mode Electrical Characteristics
Parameter
Sym
F
MAX
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
CENS
t
CENH
t
ADVS
t
ADVH
166
133
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1 See “Notes” on page 15
Min
6
0
1.5
0
0
2.4
2.3
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
Max
166
3.5
3.5
3.5
3.5
Min
7.5
0
1.5
0
0
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
Max
133
3.8
3.8
3.8
3.8
Clock frequency
Cycle time
Clock access time
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
Clock low pulse width
Address and Control setup to clock high
Data setup to clock high
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
Clock enable setup to clock high
Clock enable hold from clock high
ADV setup to clock high
ADV hold from clock high
2,3,4
2
2,3,4
2,3,4
2,3,4
5
5
6
6
6, 7
6, 8
6
6
6, 7
6, 8
6
6
6
6
Description
Conditions
ZZ > V
IH
Symbol
I
SB2
t
PDS
t
PUS
t
ZZI
t
RZZI
Min
Max
40
Units
mA
cycle
cycle
cycle
cycle
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2
2
2
0
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