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參數(shù)資料
| 型號： | AS7C252MPFS18A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 2.5V 2M x 18 pipelined burst synchronous SRAM |
| 中文描述： | 2.5V的200萬× 18管線爆裂同步SRAM |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 507K |
| 代理商： | AS7C252MPFS18A |
2/14/05, v.1.3
Alliance Semiconductor
9 of 18
AS7C252MPFS18A
Timing characteristics over operating range
Snooze Mode Electrical Characteristics
Parameter
Sym
f
Max
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
–200
–166
-133
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1 See “Notes” on page 15.
Min
–
5
–
–
0
1.5
0
–
–
0
2.0
2.0
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
0.4
0.4
0.4
Max
200
–
3.1
3.1
–
–
–
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
–
6
–
–
0
1.5
0
–
–
0
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
Max
166
–
3.5
3.5
–
–
–
3.4
3.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
–
7.5
–
–
0
1.5
0
–
–
0
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
Max
133
–
3.8
3.8
–
–
–
3.8
3.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Clock frequency
Cycle time
Clock access time
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
Clock low pulse width
Address setup to clock high
Data setup to clock high
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
2,3,4
2
2,3,4
2,3,4
2,3,4
5
5
6
6
6,7
6,8
6
6
6,7
6,8
6
6
6
6
6
6
Description
Conditions
ZZ > V
IH
Symbol
I
SB2
t
PDS
t
PUS
t
ZZI
t
RZZI
Min
Max
80
Units
mA
cycle
cycle
cycle
cycle
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
2
2
2
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C252MPFS18A-133TQC | 2.5V 2M x 18 pipelined burst synchronous SRAM |
| AS7C252MPFS18A-133TQCN | 2.5V 2M x 18 pipelined burst synchronous SRAM |
| AS7C252MPFS18A-133TQI | 2.5V 2M x 18 pipelined burst synchronous SRAM |
| AS7C252MPFS18A-133TQIN | 2.5V 2M x 18 pipelined burst synchronous SRAM |
| AS7C252MPFS18A-166TQC | 2.5V 2M x 18 pipelined burst synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C252MPFS18A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 2M x 18 pipelined burst synchronous SRAM |
| AS7C252MPFS18A-133TQCN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 2M x 18 pipelined burst synchronous SRAM |
| AS7C252MPFS18A-133TQI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 2M x 18 pipelined burst synchronous SRAM |
| AS7C252MPFS18A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 2M x 18 pipelined burst synchronous SRAM |
| AS7C252MPFS18A-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 2M x 18 pipelined burst synchronous SRAM |
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