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參數(shù)資料
| 型號： | AS7C252MNTD18A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 2.5V 2M x 18 Pipelined SRAM with NTD |
| 中文描述： | 2.5V的200萬× 18的SRAM與新臺幣流水線 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 436K |
| 代理商： | AS7C252MNTD18A |
1/17/05, V 1.2
Alliance Semiconductor
P. 15 of 18
AS7C252MNTD18A
AC test conditions
Output load: For t
LZC
, t
LZOE
, t
HZOE
, and t
HZC
, see Figure C. For all others, see Figure B.
Notes
1) For test conditions, see “AC test conditions”, Figures A, B, and C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
HZOE
is less than t
LZOE
, and t
HZC
is less than t
LZC
at any given temperature and voltage.
5) t
CH
is measured high above V
IH
, and t
CL
is measured low below V
IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to
R/
W
and
BW[a,b]
.
8) Chip select refers to
CE0
,
CE1, and CE2
.
Input pulse level: GND to 2.5V. See Figure A.
Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.
Input and output timing reference levels: 1.25V.
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+2.5
V
V
L
= V
DDQ
/2
Thevenin equivalent:
353
/1538
5 pF*
319
/1667
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+2.5V
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相關代理商/技術參數(shù) |
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| AS7C252MNTD18A-133TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 2M x 18 Pipelined SRAM with NTD |
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| AS7C252MNTD18A-133TQIN | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 2M x 18 Pipelined SRAM with NTD |
| AS7C252MNTD18A-166TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 2M x 18 Pipelined SRAM with NTD |
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