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參數資料
| 型號： | AS7C252MNTD18A-200TQIN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2.5V 2M x 18 Pipelined SRAM with NTD |
| 中文描述： | 2M X 18 ZBT SRAM, 3.2 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁數： | 1/18頁 |
| 文件大?。?/td> | 436K |
| 代理商： | AS7C252MNTD18A-200TQIN |
January 2005
Copyright Alliance Semiconductor. All rights reserved.
AS7C252MNTD18A
1/17/05, V 1.2
Alliance Semiconductor
P. 1 of 18
2.5V 2M × 18 Pipelined SRAM with NTD
TM
Features
Organization: 2,097,152 words × 18 bits
NTD
architecture for efficient bus operation
Fast clock speeds to 200 MHz
Fast clock to data access: 3.2/3.5/3.8 ns
Fast OE access time:
3.2/3.5/3.8 ns
Fully synchronous operation
Pipelined mode
Common data inputs and data outputs
Asynchronous output enable control
Available in 100-pin TQFP packages
Byte write enables
Clock enable for operation hold
Multiple chip enables for easy expansion
2.5V core power supply
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
Selection guide
-200
5
200
3.2
450
170
90
-166
6
166
3.5
400
150
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
W
register
Burst logic
D
Q
CLK
Output
Register
DQ[a,b]
21
21
CLK
CEN
CE0
CE1
CE2
A[20:0]
OE
CLK
Control
logic
CLK
Data
Input
Register
D
Q
CLK
18
18
OE
2 M x 18
SRAM
Array
R/W
BWa
DQ[a,b]
BWb
CLK
Q
D
ADV / LD
LBO
addr. registers
Write delay
21
ZZ
CLK
18
18
18
18
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相關代理商/技術參數 |
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| AS7C252MNTF18A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 2M x 18 Flowthrough SRAM with NTD |
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