參數(shù)資料
型號: AS7C251MNTF18A-85TQCN
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD
中文描述: 1M X 18 ZBT SRAM, 8.5 ns, PQFP100
封裝: 14 X 20 MM, LEAD FREE, TQFP-100
文件頁數(shù): 15/18頁
文件大?。?/td> 433K
代理商: AS7C251MNTF18A-85TQCN
AS7C251MNTF18A
12/23/04, v 1.1
Alliance Semiconductor
P. 15 of 18
AC test conditions
Notes:
1) For test conditions, see “AC test conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
HZOE
is less than t
LZOE
and t
HZC
is less than t
LZC
at any given temperature and voltage.
5) t
CH
measured high above V
IH
and t
CL
measured as low below V
IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to
R/
W
and
BW[a,b]
.
8) Chip select refers to
CE0
,
CE1
, and
CE2
.
Undefined/don’t are
Falling input
Rising input
Output load: For t
LZC
, t
LZOE
, t
HZOE
, and t
HZC
, see Figure C. For all others, see Figure B.
Input pulse level: GND to 2.5V. See Figure A.
Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.
Input and output timing reference levels: 1.25V.
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+2.5V
V
L
= V
DDQ
/2
Thevenin equivalent:
353
/1538
5 pF*
319
/1667
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+2.5V
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AS7C251MNTF18A-85TQI 2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD
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