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參數(shù)資料
| 型號： | AS7C251MNTF18A-10TQIN |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD |
| 中文描述： | 1M X 18 ZBT SRAM, 10 ns, PQFP100 |
| 封裝： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 433K |
| 代理商： | AS7C251MNTF18A-10TQIN |
December 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C251MNTF18A
12/23/04, v 1.1
Alliance Semiconductor
P. 1 of 18
2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD
TM
Features
Organization: 1,048,576 words × 18 bits
NTD
architecture for efficient bus operation
Fast clock to data access: 7.5/8.5/10 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous operation
Flow-through mode
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Clock enable for operation hold
Multiple chip enables for easy expansion
2.5V core power supply
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
Selection guide
-75
8.5
7.5
275
90
60
-85
10
8.5
250
80
60
-10
12
10
230
80
60
Units
ns
ns
mA
mA
mA
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
W
register
burst logic
D
Q
CLK
Output
buffer
DQ [a,b]
20
20
CLK
CEN
CE0
CE1
CE2
A[19:0]
OE
Control
logic
CLK
Data
input
register
D
Q
CLK
18
18
OE
1M x 18
SRAM
array
R/W
DQ [a,b]
BWa
BWb
CLK
Q
D
ADV / LD
LBO
ZZ
addr. registers
Write delay
20
CLK
18
18
18
18
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| AS7C251MNTF18A-75TQC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD |
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