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參數資料
| 型號： | AS7C1026-20TC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 |
| 中文描述： | 64K X 16 STANDARD SRAM, 20 ns, PDSO44 |
| 封裝： | 18.40 X 10.20 MM, TSOP2-44 |
| 文件頁數： | 6/10頁 |
| 文件大小： | 239K |
| 代理商： | AS7C1026-20TC |
S
6
ALLIANCE SEMICONDUCTOR
DID 11-20011-A. 5/22/00
AS7C1026
AS7C31026
Data retention characteristics (over the operating range)
13
Parameter
V
CC
for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Input leakage current
Data retention waveform
AC test conditions
- Output load: see Figure B or Figure C, except as noted.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 2V data retention applies to commercial temperature range operation only.
14 C=30pF, except all high Z and low Z parameters where C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Condtions
, Figures A, B, and C.
These parameters are specified with C
L
= 5pF, as in Figures B or C. Transition is measured ± 500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Symbol
V
DR
I
CCDR
t
CDR
t
R
|I
LI
|
Test conditions
Min
2.0
–
0
t
RC
–
Max
–
500
–
–
1
Unit
V
μ
A
ns
ns
μ
A
V
CC
= 2.0V
CE
≥
V
CC
–0.2V
V
IN
≥
V
CC
–0.2V or
V
IN
≤
0.2V
V
CC
CE
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
2.0V
V
IH
V
IH
V
DR
255W
C(14)
320W
GND
+3.3V
Figure C: 3.3V Output load
168W
Thevenin Equivalent:
D
OUT
+1.728V (5V and 3.3V)
255W
C(14)
480W
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
D
OUT
D
OUT
相關PDF資料 |
PDF描述 |
|---|---|
| AS7C31026-20JC | 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85 |
| AS7C31026-20TC | 8-Bit Parallel-Load Shift Registers 16-TSSOP -40 to 85 |
| AS7C31026-20TI | 8-Bit Parallel-Load Shift Registers 16-TSSOP -40 to 85 |
| AS7C31026-10 | 5V/3.3V 64Kx6 CMOS SRAM |
| AS7C31026-10BC | 5V/3.3V 64Kx6 CMOS SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AS7C1026-20TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V / 3.3V 64KX16 CMOS SRAM |
| AS7C1026-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| AS7C1026-25JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| AS7C1026-25TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| AS7C1026A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 64K X 16 CMOS SRAM |
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