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參數(shù)資料
| 型號(hào)： | AS7C1025A-12TJC |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| 中文描述： | 128K X 8 STANDARD SRAM, 12 ns, PDSO32 |
| 封裝： | 0.300 INCH, SOJ-32 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | AS7C1025A-12TJC |
AS7C1025A
AS7C31025A
2/6/01; V0.9
Alliance Semiconductor
P. 2 of 8
Functional description
The AS7C1025A and AS7C31025A are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 3/3/4/5 ns are ideal for
high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When
CE
is high the devices enter standby mode. The standard AS7C1025A is guaranteed not to exceed 55 mW power consumption in
standby mode. Both devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data on the input pins I/O0-I/O7 is written on the rising
edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been
disabled with
output enable (
OE
) or write enable
(
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chips drive I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1025A) or 3.3V supply (AS7C31025A). The
AS7C1025A and AS7C31025A are packaged in common industry standard packages.
Absolute maximum ratings
NOTE: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t Care, L = Low, H = High
Parameter
Device
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
AS7C1025A
V
t1
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
–0.50
+7.0
V
AS7C31025A
–0.50
+5.0
V
Voltage on any pin relative to GND
–0.50
V
CC
+ 0.5
1.0
V
Power dissipation
–
W
o
C
o
C
Storage temperature (plastic)
–65
+150
Ambient temperature with V
CC
applied
DC current into outputs (low)
–55
+125
–
20
mA
CE
WE
OE
Data
Mode
H
X
X
High Z
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
L
H
H
High Z
L
H
L
D
OUT
D
IN
L
L
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1025A-12TJI | 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025A-15JC | High Speed CMOS Logic Quad 2-Input AND Gates 14-TSSOP -55 to 125 |
| AS7C1025A-15JI | 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025A-15TC | 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025A-15TI | 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1025A-12TJI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025A-15JC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025A-15JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025A-15TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025A-15TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
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