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參數(shù)資料
| 型號： | AS7C1024-20TJI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| 中文描述： | 128K X 8 STANDARD SRAM, 20 ns, PDSO32 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 208K |
| 代理商： | AS7C1024-20TJI |
November 2000
Copyright 2000 Alliance Semiconductor. All rights reserved.
AS7C1024
AS7C31024
11/29/00
ALLIANCE SEMICONDUCTOR
1
5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
Features
AS7C1024 (5V version)
AS7C31024 (3.3V version)
Industrial and commercial temperatures
Organization: 131,072 words × 8 bits
High speed
- 10/12/15/20 ns address access time
- 5/6/8/10 ns output enable access time
Low power consumption: ACTIVE
- 825 mW (c) / max @ 12 ns
- 360 mW (AS7C31024) / max @ 12 ns
Low power consumption: STANDBY
- 55 mW (AS7C1024) / max CMOS
- 36 mW (AS7C31024) / max CMOS
2.0V data retention
Easy memory expansion with CE1, CE2, OE inputs
TTL/LVTTL-compatible, three-state I/O
32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP I
- 8 × 13.4 mm sTSOP I
ESD protection
≥
2000 volts
Latch-up current
≥
200 mA
Logic block diagram
512
×
256
×
8
Array
(1,048,576)
S
Input buffer
A
A
A
A
A
A
A
I/O0
I/O7
CE1
CE2
OE
Column decoder
R
Control
circuit
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
GND
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE
A13
A8
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A
A
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
A15
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A3
A2
A0
32-pin TSOP I
(8 x 20mm)
I/O1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
Selection guide
Shaded areas contain advance information.
AS7C1024-10
AS7C31024-10
10
5
150
100
10
10
AS7C1024-12
AS7C31024-12
12
6
140
90
10
10
AS7C1024-15
AS7C31024-15
15
8
125
80
10
10
AS7C1024-20
AS7C31024-20
20
10
110
75
15
15
Unit
ns
ns
mA
mA
mA
mA
Maximum address access time
Maximum output enable access time
Maximum operating current
AS7C1024
AS7C31024
AS7C1024
AS7C31024
Maximum CMOS standby current
相關PDF資料 |
PDF描述 |
|---|---|
| AS7C31024-20JC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024-20JI | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-TSSOP -55 to 125 |
| AS7C31024-20TC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024-20TI | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| AS7C31024-20TJI | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-TSSOP -55 to 125 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1024-20TPC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| AS7C1024-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| AS7C1024-25PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| AS7C1024-25TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| AS7C1024-25TJC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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