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| 型號： | AS7C1024-15JI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| 中文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 208K |
| 代理商： | AS7C1024-15JI |
6
ALLIANCE SEMICONDUCTOR
11/29/00
AS7C1024
AS7C31024
Data retention characteristics (over the operating range)
13
Parameter
V
CC
for data retention
Data retention waveform
AC test conditions
– 5V output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
Notes
1
2
3
4
5
6
7
8
9
10 CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 2V data retention applies to commercial temperature operating range only.
14 C=30pF, except all high Z and low Z parameters, C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE1 is required to meet I
SB
specification.
This parameter is sampled and not 100% tested.
For test conditions, see
AC Test Condtions
, Figures A, B, and C.
t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE1 and OE are Low and CE2 is High for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Symbol
VDR
Test conditions
Device
Min
2.0
–
–
0
t
RC
–
Max
–
5
1
–
–
1
Unit
V
mA
mA
ns
ns
μA
V
CC
= 2.0V
CE1
≥
V
CC
–0.2V or
CE2
≤
0.2V
V
IN
≥
V
CC
–0.2V or
V
IN
≤
0.2V
Data retention current
ICCDR
AS7C1024
AS7C31024
Chip deselect to data retention time
Operation recovery time
Input leakage current
tCDR
tR
| ILI |
V
CC
CE1
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
2.0V
V
IH
V
IH
V
DR
255W
C(14)
320W
D
OUT
GND
+3.3V
168W
Thevenin equivalent:
D
OUT
+1.728V (5V and 3.3V)
Figure C: 3.3V Output load
255W
C(14)
480W
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1024-15TC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| AS7C1024-15TI | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| AS7C1024-15TJC | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| AS7C1024-15TJI | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| AS7C1024-20 | 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C1024-15PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| AS7C1024-15TC | 制造商:Alliance Memory Inc 功能描述: |
| AS7C1024-15TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
| AS7C1024-15TJC | 制造商:Alliance Memory Inc 功能描述:Static RAM, 128Kx8, 32 Pin, Plastic, SOJ |
| AS7C1024-15TJI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout) |
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