參數(shù)資料
型號(hào): AS4LC4M4
英文描述: 16384Kbits 4M x 4 Replacement with DSCC 5962-n/a | DRAM
中文描述: 16384Kbits 4米× 4置換籍局5962氮/ 1 |內(nèi)存
文件頁數(shù): 3/15頁
文件大?。?/td> 265K
代理商: AS4LC4M4
AS4LC4M4E0
AS4LC4M4E1
4/11/01; V1.1
Alliance Semiconductor
P. 3 of 15
Logic block diagram for 4K refresh
Logic block diagram for 2K refresh
Recommended operating conditions
Parameter
V
IL
min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
Absolute maximum ratings
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
CC
GND
3.0
3.3
3.6
V
0.0
0.0
0.0
V
Input voltage
V
IH
V
IL
2.0
–0.5
V
CC
+0.5V
0.8
V
V
Ambient operating temperature
Commercial
T
A
0
70
°C
Industrial
-40
85
Symbol
Min
Max
Unit
Input voltage
V
in
V
DQ
V
CC
T
STG
T
SOLDER
-1.0
4.6
V
Input voltage (DQs)
-1.0
4.6
V
Power supply voltage
-1.0
4.6
V
Storage temperature (plastic)
-55
+150
°C
o
C × sec
Soldering temperature × time
260 × 10
RAS
clock
generator
R
c
4096 × 1024 × 4
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
V
CC
GND
A
R
Column decoder
Data
I/O
buffers
OE
RAS
CAS
WE
clock
generator
WE
I/O0 to I/O3
CAS
clock
generator
RAS
clock
generator
R
c
2048 × 2048 × 4
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
V
CC
GND
A
R
Column decoder
Substrate bias
generator
Data
I/O
buffers
OE
RAS
CAS
WE
clock
generator
WE
I/O0 to I/O3
CAS
clock
generator
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