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參數(shù)資料
| 型號： | AS3588AP |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 路由/交換 |
| 英文描述： | DIGITAL TIME/SPACE CROSSPOINT SWITCH |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 98K |
| 代理商： | AS3588AP |
Data Sheet
AS3588A
Rev. 3.1
Page 3 of 15
July 1999
26 - 27
23 - 26
IP
A1, S1, A2, S2
Address Decoder Inputs
These active high inputs are provided for larger non blocking digital
switching matrixes with cascaded AS 3588 devices.
30
27
IP
C/D
Control/ Data Select Input
The signal on this control input defines whether the data on the data
bus should be interpreted as opcode or as data. During a write
operation a low signal defines the bus content as data and a high
signal defines it as opcode. During a read operation this input acts as
multiplexing control: OR1 is selected by a low signal; OR2 is selected
by a high signal.
31
28
Power
VSS
Negative Supply Voltage
32
29
IP
RESET
Reset Input
This active low input is used for starting the system initialization. This
pin is strobed at the first timeslot. The initialization routine takes one
time frame period independent of the reset pulse width and is
continued for another time frame when the signal is kept low during
strobe. Initialization disables the output drivers of the microprocessor
interface; The Connection Memory is cleared and the PCM output
drivers are disabled.
33 - 34
30 - 31
IP
CS1, CS2
Chip Select Inputs
These are the inputs for the active low chip selects on the
microprocessor interface. The two inputs are provided for flexible
decoding.
35
32
IP
WR
Write Input
This active low input is for the write signal on the microprocessor
interface. The data bus is strobed on the rising edge.
36
34
IP
RD
Read Input
This active low input is for the read signal on the microprocessor
interface. The databus is updated on the falling edge.
37 - 40
35 - 38
OP
OUTPCM 7 to
OUTPCM 4
PCM Outputs 7 to 4
These are open drain outputs for four primary rate PCM output
streams.
Functional Description
The AS3588A is a digital time / space crosspoint
switching matrix and is designed to switch data from
eight primary rate input ports operating at 2048 kbit/s
to eight primary rate 2048 kbit/s output ports.
Simultaneously it allows its controlling microprocessor
to read PCM output channels or write to PCM output
channels
(Messaging).
AS3588A looks like a memory mapped peripheral de-
vice that is controlled by six different instructions. It
can write to AS3588A commands to establish or
release switched connections between PCM input
channels and PCM output channels or to transmit
messages on specific PCM output channels. By
reading from the AS3588 the microprocessor can
receive messages from PCM output channels or from
To
the
Microprocessor
the channel 0 of the input ports or check which
connections have been made by reading the
connection memory.
By integrating both switching and interprocessor
communications the AS3588A is ideally suited for dis-
tributed processing in digital switching systems.
Hardware Description
Timing
All AS3588 internal timing is derived from the 4.096
MHz master clock signal CK and the 8 kHz frame syn-
chronization signal SYNC. Different time bases for the
serial to parallel PCM input converter and the parallel
to serial PCM output converter are generated internally
which compensate for the internal input/output
conversion delays. They are synchronized to a preset
number in order to restore the channel and bit se-
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