參數(shù)資料
型號(hào)： AS3502
廠商： AUSTRIAMICROSYSTEMS AG
元件分類(lèi)： 圓形連接器
英文描述： Circular Connector; No. of Contacts:3; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:22; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:22-9 RoHS Compliant: No
中文描述： 13位線性編解碼器特征與模擬前端模塊
文件頁(yè)數(shù)： 8/29頁(yè)
文件大?。?/td> 364K
代理商： AS3502
REV. M
Page 8
September 1998
AS3502
PCM Level
8-Bit A-Law Format
D
6
5
4
16-Bit Linear Format
D
1
1
0
D
7
D
D
D
3
D
2
D
1
D
0
D
1
5
D
1
4
D
1
3
D
1
2
D
1
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
VIN =
VIN =
VIN =
VIN =
x: not used
The interface supports short and long strobe
synchronisation modes and full duplex synchronous
operations of both receive and transmit section. PCM
data is written into the transmit register and shifted
out in 8 or 16 clock cycles by the transmit shift
register. In the receive direction serial input 8 or 16
samples are converted into parallel format by the
receive shift register and hereafter buffered in the
receive latch. This double buffered hardware I/O
scheme guarantees minimum port latency and
increased channel service time. Both shift registers
have separate strobe signals for asynchronous time
slot operation of transmit and receive channel and are
clocked by a common shift clock signal that may vary
from 64 kHz up to 4.096 MHz and that must be locked
to the master clock. The strobe signals have to be
synchronised to the shift clock and should have a
repetition rate of 8 kHz. ±50 ppm.
Short Strobe Mode
This is the default mode on powering up the device.
The transmit and receive strobe inputs must be one
bit shift clock long and have to be High during a falling
edge of the respective bit shift clocks (see PCM
Timing Diagramme) In the transmit section the next
rising edges of SCLK enable the TXD output buffer
and shift out PCM data bits. The falling edge of the
last bit shift clock SCLK disables the TXD output
buffer. In the receive section the next falling edge of
SCLK shifts in PCM data bits at RXD.
Long Strobe Mode
The serial port enters the long strobe mode if both
strobe pulses (TXS, RXS) are more than three bit
clock periods long (See PCM Timing Diagramme). In
the transmit section the next rising edge of SCLK or
TXS, whichever comes later, clocks out the first bit.
The effect of the transmit strobe occurring after the
shift clock is to shorten the first bit at the TXD output.
The following rising edges of the SCLK shift out the
remaining data bits. The TXD output is disabled by
the last falling SCLK edge or by the TXS signal going
Low, whichever comes later. In the receive section a
rising edge on the receive strobe input RXS will initi-
ate the PCM data on RXD pin to be shifted into the
receive shift register with the falling edges of SCLK.
+ Full Scale
+0-Code
-0-Code
- Full Scale
1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 x
1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 x
0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x
0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x
x
x
x
x
x
x
x
x
Serial Control Interface
The internal operation of AS3502 is controlled by a 4-
wire serial port that is designed to write and read back
control and status information from any serial micro-
processor port. It consists of a 16 bit shift register with
8 address bits and 8 data bits. The first byte is the
Address Byte that is clocked in serially by asserting
the CS line for 8 clock cycles. The MSB address bit
in the address field defines whether the data transfer
is a write or a read operation. The second byte is the
Command Data Byte that is clocked in by keeping
CS Low for another 8 clock cycles. The address
decoder latches the address bits received into a
register after 8 clock cycles. It operates fully
autonomously and constantly cycles through 3 states:
Load address decoder
Calculate address and type of data transfer
Data transfer
After decoding the data byte is latched into the de-
coded register during a write operation or retrieved
from the selected register during a read operation.
Data is retrieved by asserting the CS line and by
shifting 8 address bits into the input shift register
through SDI. The next 8 clock cycles shift out the data
byte through SDO. The full shift register is shifted out
where the 8 MSB bits are shifted out as Hi-Z.
Data states on the SDO line can only change with the
falling edge of SCL. Data on the SDI line is shifted in
with the rising edge of SCL.
All commands are preceded by the start condition,
which is a High to Low transition of the CS line. The
AS3502 continuously monitors this line for the start
condition and does not respond to any command until
this condition has been met. CS may either be kept
Low for 16 clock cycles or may go High after 8 clock
cycles and go Low again for the next 8 clock cycles
when programming different register locations.
All communications are terminated by a stop condi-
tion, which is a Low to High transition of CS after 16
shift clock cycles. The stop condition is also used to
place the AS3502 serial control interface in the
standby power mode.
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AS3502 EB 制造商:AMS 功能描述:BOARD EVAL FOR AS3502
AS3502-EB 制造商:ams 功能描述:AS3501 Evaluation Board
AS3502-EQFP 功能描述:IC HEADPHONE NOISE-CANCEL 32-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 濾波器類(lèi)型:連續(xù)時(shí)間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR)
AS3502-EQFP-500 功能描述:IC HEADPHONE NOISE-CANCEL 32-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 濾波器類(lèi)型:連續(xù)時(shí)間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR)
AS350-MSF 制造商:Autec Power Systems 功能描述:AC/DC Power Supply Quad-OUT 3.3V/5V/12V/-12V 20A/20A/18A/0.8A 350W
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