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參數(shù)資料
| 型號(hào)： | AS1975-T |
| 廠商： | ams |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR QUAD O-D 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 通用 |
| 元件數(shù)： | 4 |
| 輸出類型： | CMOS，開路漏極，滿擺幅 |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V |
| 電壓 - 輸入偏移（最小值）： | 6mV @ 5.5V |
| 電流 - 輸入偏壓（最小值）： | 1pA @ 5.5V |
| 電流 - 靜態(tài)（最大值）： | 64µA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 80dB CMRR，80dB PSRR |
| 傳輸延遲（最大）： | 400ns |
| 磁滯： | ±3mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
www.austriamicrosystems.com
Revision 1.02
12 - 18
AS1970
Data Sheet - Ap p lica tio n In fo r m a tio n
Hysteresis Band
Internal hysteresis creates two trip points (shown in Figure 20): rising input voltage (VTHR) and falling input voltage
(VTHF). The area between the trip points is the hysteresis band (VHB). When the comparator input voltages are equiva-
lent, the hysteresis effectively causes one comparator input to move quickly past the other, thus taking the input out of
the region where oscillation occurs.
In Figure 20 REF has a fixed voltage applied and IN+ is varied. If the inputs are reversed the output will be inverted.
Figure 20. Threshold Hysteresis Band
Zero-Crossing Detector
Figure 21 shows the AS1970 in a zero-crossing detector circuit. The inverting input is connected to ground, and the
non-inverting input is connected to a 100mVp-p signal source. As the signal at the non-inverting input crosses 0V, the
signal at OUT changes states.
Figure 21. Zero-Crossing Detector
Logic Level Translator
The comparators can be used as a 5V/3V logic translator as shown in Figure 22. The circuit in Figure 22 converts 5V-
to 3V-logic levels, and provides the full 5V logic-swing without creating overvoltage on the 3V logic inputs. When the
comparator is powered by a 5V supply, RPULLUP for the open-drain output should be connected to the +3V supply volt-
age.
For 3V-to-5V logic-level translations, connect the +3V supply voltage to VCC and the +5V supply voltage to RPULLUP.
Figure 22. Logic Level Translator
IN+
OUT
VTHR
VTHF
REF
Thresholds
Hysteresis
Band
VHB
5
VEE
1
OUT
100mVp-p
AS1970
4
IN-
3
IN+
2
VCC
–
+
–
+
AS1971
RPullup
+5/+3V
Logic Out
+3/+5V
+5/+3V
Logic In
100k
Ω
100k
Ω
+3/+5V
4
IN-
5
VEE
3
IN+
1
OUT
2
VCC
–
+
–
+
ams
AG
Technical
content
still
valid
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