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| 型號： | AS1526-BSOT |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | ADC |
| 英文描述： | 10-bit ADC 1-CH, 73ksps intRef; Package Type: SOIC-8 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 307K |
| 代理商： | AS1526-BSOT |
wwwams.com
Revision 1.4
11 - 20
AS1526/AS1527
Datasheet
- Detailed Description
8.1.1 Input Protection
Internal protection diodes clamp the analog input to V
DD
and GND, allowing the input to swing from(GND - 0.3V) to (V
DD
+ 0.3V) without
damage. However, for accurate conversions near full scale, the input must not exceed V
DD
by more than 50mV, or be lower than GND by 50mV.
Note:
If the analog input exceeds the supply by 50mV, limt the input current to 2mA.
8.2 Track/Hold
In track mode, the analog signal is acquired and stored in the internal hold capacitors. During acquisition, the analog input at pin AIN charges
capacitor C
HOLD
(see Figure 24 on page 10)
. Bringing CSN low ends the acquisition interval and the charge on C
HOLD
represent the sampled
input voltage.
In hold mode, the T/H switches are opened thus the input is disconnected fromthe capacitor C
HOLD.
During this mode the successive
approximation is performed which in turn forms a digital representation of the analog input signal. At the end of the conversion, the input side of
the in meantime discharged C
HOLD
switches back to AIN, and C
HOLD
charges to the input signal again.
The maximumtime for the T/H to acquire a signal (t
ACQ
) is a function of how quickly its input capacitance is charged. t
ACQ
increases
proportionally to the input signal’s impedance, and at higher impedances more time must be allowed between conversions. t
ACQ
is also the
mnimumtime needed for the signal to be acquired, and is calculated by:
t
ACQ
= 7(R
S
+ R
IN
) x 21pF
(EQ 1)
Where:
R
IN
= 4.5k
Ω
R
S
= the input signal’s source impedance.
t
ACQ
is never less than 1.5μs. Source impedances < 1k
Ω
do not significantly affect the AC performance of the devices.
Note:
Higher source impedances can be used if a 0.01μF capacitor is connected to the analog input. Note that the input capacitor forms an
RC filter with the input source impedance, limting the devices’ input signal bandwidth.
8.3 External Clock
The AS1526/AS1527 do not require an external clock for analog-to-digital data conversion. This allows the mcroprocessor to read back the
conversion results at any clock rate fromup to 2.1MHz at any time. The clock duty cycle is unrestricted if each clock phase is at least 200ns.
Note:
The external clock must not be run while a conversion is in progress.
8.4 Timing and Control
Conversion-start and data-read operations are controlled by digital inputs CSN and SCLK. Refer to Figures
25
-
27
(see page 12
) for graphical
timng and control information.
The falling edge on pin CSN initiates a conversion sequence:
1. The T/H stage holds the voltage at pin AIN, and the A/D conversion begins.
2. Pin DOUT changes fromhigh-impedance to logic-low SCLK must be kept low during the conversion.
3. The internal SAR stores the data during the conversion process.
4. Pin DOUT going high indicates the conversion process has completed.
5. The rising edge of pin DOUT can be used as a framng signal.
6. SCLK shifts the data out of this register any time after the conversion is complete.
7. DOUT transitions on the falling edge of pin SCLK.
8. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 10 data bits
and one leading high-bit or 10 data bits, two sub bits, and one leading high-bit, at least 11 or 13 falling clock edges are needed to shift
out these bits, respectively.
9. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CSN, produce trailing zeros
at DOUT and have no effect on the conversion process.
10. For mnimumcycle time, clock out the data with 10.5 clock cycles at full speed using the rising edge of DOUT as the EOC signal. Pull
CSN high after reading the conversions LSB. After the specified mnimumtime (t
CS
) CSN can be pulled low to initiate the next conver-
sion.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS1526BSOU | 制造商:ams 功能描述:IC ADC 10BIT 73KSPS SOIC-8 制造商:ams 功能描述:IC, ADC, 10BIT, 73KSPS, SOIC-8, Resolution (Bits):10bit, Sampling Rate:73kSPS, Supply Voltage Type:Single, Supply Voltage Min:2.7V, Supply Voltage Max:3.6V, Supply Current:1.4mA, Digital IC Case Style:SOIC, No. of Pins:8, MSL:- , RoHS Compliant: Yes 制造商:ams 功能描述:SOIC 8 |
| AS1526-BSOU | 功能描述:IC A/D 10-BIT 1-CH 73K 8-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AS1527 | 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:10-Bit, Single Supply, Low-Power, 73ksps A/D Converters |
| AS1527-BSOT | 功能描述:IC ADC 10BIT 1CH 73K 8-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AS1527BSOU | 制造商:AMS 功能描述:IC ADC 10BIT 73KSPS SOIC-8 制造商:AMS 功能描述:IC, ADC, 10BIT, 73KSPS, SOIC-8; Resolution (Bits):10bit; Sampling Rate:73kSPS; Supply Voltage Type:Single; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; Supply Current:1.4mA; Digital IC Case Style:SOIC; No. of Pins:8; DNL:1LSB ;RoHS Compliant: Yes |
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