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參數(shù)資料
| 型號： | AS1500-Z-T |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 256 steps, SPI 10kΩ, DigiPot; Package Type: SOIC-8; Resistance: 10,00 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 398K |
| 代理商： | AS1500-Z-T |
www.austriamicrosystems.com
Revision 1.01
7 - 14
AS1500
Data Sheet
- Electrical Characteristics
AS150x – SPECIFICATIONS
V
CC
= 3V±10% or 5V±10%, V
A
= V
CC
, V
B
= 0V, –40oC
≤
T
A
≤
+125oC unless otherwise noted.
t
S
_50k
VW Settling Time
R
WB
= 50k
Ω
, V
A
= V
CC
, V
B
= 0V,
±1% Error Band
R
WB
= 100k
Ω
, V
A
= V
CC
, V
B
= 0V,
±1% Error Band
R
WB
= 50k
Ω
, f =1kHz
R
WB
= 100k
Ω
, f =1kHz
9
μs
t
S
_100k
18
μs
e
NWB
_50k
Resistor Noise Voltage
20
nV/
√
Hz
e
NWB
_100k
29
nV/
√
Hz
1. Typicals represent average readings at 25oC and V
CC
= 5V.
2. Wiper is not connected. I
AB
= 70μA for the 50k
Ω
version and 35μA for the 100k
Ω
version.
3. All Tempcos are guaranteed by design and not subject to production test.
4. Terminal A is not connected. I
W
= 70μA for the 50k
Ω
version and 35μA for the 100k
Ω
version.
5. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6. All capacitances are guaranteed by design and not subject to production test. Resistor-terminal capacitance
tests are measured with 2.5V bias on the measured terminal. The remaining resistor terminals are left open cir-
cuit.
7. Worst-case supply current consumed when input logic level at 2.4V, standard characteristic of CMOS logic.
8. P
DISS
is calculated from (I
DD
×V
CC
). CMOS logic level inputs result in minimum power dissipation.
9. All dynamic characteristics are guaranteed by design and not subject to production test. All dynamic characteris-
tics use V
CC
=5V.
Table 5. Switching Characteristics
Symbol
Parameter
Conditions
Min
Typ
1
1. Typicals represent average readings at 25oC and V
CC
=5V.
2. Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with
2.5V bias on the measured terminal. The remaining resistor terminals are left open circuit.
3. See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1ns
(10% to 90% of V
CC
) and timed from a voltage level of 1.6V. Switching characteristics are measured using
V
CC
=3V or 5V. To avoid false clocking, a minimum input logic slew rate of 1V/μs should be maintained.
Max
Unit
Switching Characteristics
2
3
t
CH
, t
CL
Input Clock Pulsewidth
Clock Level High or Low
50
ns
t
DS
Data Setup Time
5
ns
t
DH
Data Hold Time
5
ns
t
CSS
CSN Setup Time
10
ns
t
CSWH
CSN High Pulsewidth
10
ns
t
CSWL
CSN Low Pulsewidth
100
ms
t
CSH
CK Fall to CSN Rise
Hold Time
0
ns
t
CS1
CSN Rise to Clock Rise
Setup
10
ns
Table 4. Electrical Characteristics – 50k and 100k Versions
Symbol
Parameter
Conditions
Min
Typ
1
Max
Units
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