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參數(shù)資料
| 型號： | ARA2004S23P1 |
| 廠商： | ANADIGICS INC |
| 元件分類： | 放大器 |
| 英文描述： | RF/MICROWAVE NARROW BAND HIGH POWER AMPLIFIER |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 261K |
| 代理商： | ARA2004S23P1 |
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
13
ARA2004
APPLICATION INFORMATION
Transmit Enable / Disable
The ARA2004 includes two amplification stages that
each can be shut down through external control pins
Vg1 and Vg2 (pins 6 and 23, respectively.) By
applying a slightly positive bias of typically +1.0 Volts,
the amplifier is enabled. In order to disable the
amplifier, the control pin needs to be pulled to
ground.
A practical way to implement the necessary control
is to use bias resistor networks similar to those
shown in the test circuit schematic (Figure 4.) Each
network includes a resistor shunted to ground that
serves as a pull-down to disable the amplifier when
no control voltage is applied. When a positive voltage
is applied, the network acts as a voltage divider that
presents the required +1.0 Volts to enable the
amplifier. By selecting different resistor values for
the voltage divider, the network can accommodate
different control voltage inputs.
The Vg1 and Vg2 pins may be connected together
directly, and controlled through a single resistor
network from a common control voltage.
Amplifier Bias Current
The ISET pins (7 and 22) set the bias current for the
amplification stages. Grounding these pins results
in the maximum possible current. By placing a
resistor from the pin to ground, the current can be
reduced. The recommended bias conditions use
the configuration shown in the test circuit schematic
in Figure 4.
Thermal Layout Considerations
The device package for the ARA2004 features an
exposed paddle on the bottom of the package body.
Use of the paddle is an integral part of the device
design. Soldering this paddle to the ground plane of
the PC board will ensure the lowest possible thermal
resistance for the device, and will result in the longest
MTF (mean time to failure.)
A PC board layout that optimizes the benefits of the
paddle is shown in Figure 18. The via holes located
under the body of the device must be plated through
to a ground plane layer of metal, in order to provide a
sufficient heat sink. The recommended solder mask
outline is shown in Figure 19.
Figure 18: PC Board Layout
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