參數(shù)資料
型號(hào): APX810-44SR-G-7
廠商: DIODES INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO3
封裝: GREEN, SOT-23R, 3 PIN
文件頁(yè)數(shù): 4/8頁(yè)
文件大?。?/td> 128K
代理商: APX810-44SR-G-7
APX809/810
3-PIN MICROPROCESSOR RESET CIRCUITS
APX809/810 Rev. 2
4 of 8
JANUARY 2008
www.diodes.com
Diodes Incorporated
Typical Application Circuit
APX8XX
GND
RESET
(RESET)
V
CC
Microprocessor
V
CC
GND
RESET
INPUT
V
CC
CIN
100nF
Function Description
A microprocessor’s (P’s) reset input starts the P in a known
state. The APX809/810 assert reset to prevent code-execution
errors during power-up, power-down, or brownout conditions.
They assert a reset signal whenever the VCC supply voltage
declines below a preset threshold, keeping it asserted for at least
240ms after VCC has risen above the reset threshold. The
APX809/810 have a push-pull output stage.
Applications Information
Negative-Going VCC Transients
In addition to issuing a reset to the P during power-up,
power-down, and brownout conditions, the APX809/810 are
relatively immune to short-duration negative-going VCC transients
(glitches).
The APX809/810 do not generate a reset pulse. The graph was
generated using a negative going pulse applied to VCC, starting
0.5V above the actual reset threshold and ending below it by the
magnitude indicated (reset comparator overdrive). The graph
indicates the maximum pulse width a negative going VCC
transient can have without causing a reset pulse. As the
magnitude of the transient increases (goes farther below the
reset threshold), the maximum allowable pulse width decreases.
Typically, a VCC transient that goes 100mV below the reset
threshold and lasts 100s or less will not cause a reset pulse. A
0.1F bypass capacitor mounted as close as possible to the VCC
pin provides additional transient immunity.
Ensuring a Valid Reset Output
Down to VCC = 0
RESET is guaranteed to be a logic low for V
CC > 1V. Once VCC
exceeds the reset threshold, an internal timer keeps
RESET
low for the reset timeout period; after this interval,
RESET
goes high.
If a brownout condition occurs (VCC dips below the
RESET reset threshold), RESET goes low. Any time V
CC
goes below the reset threshold, the internal timer resets to zero,
and
RESET goes low. The internal timer starts after V
CC
returns above the reset threshold, and
RESET remains low
for the reset timeout period.
When VCC falls below 1V, the APX809
RESET output no
longer sinks current—it becomes an open circuit. Therefore,
high-impedance CMOS logic inputs connected to
RESET can
drift to undetermined voltages.
This presents no problem in most applications since most P and
other circuitry is inoperative with VCC below 1V. However, in
applications where
RESET must be valid down to 0V, adding a
pull down resistor to
RESET causes any stray leakage
currents to flow to ground, holding
RESET low. R1’s value is
not critical; 100k are large enough not to load
RESET and
small enough to pull
RESET to ground. For the APX810 if
RESET is required to remain valid for V
CC < 1V.
Benefits of Highly Accurate Reset Threshold
Most P supervisor ICs has reset threshold voltages between 5%
and 10% below the value of nominal supply voltages. This
ensures a reset will not occur within 5% of the nominal supply,
but will occur when the supply is 10% below nominal. When using
ICs rated at only the nominal supply ±5%, this leaves a zone of
uncertainty where the supply is between 5% and 10% low, and
where the reset may or may not be asserted.
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