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參數(shù)資料
| 型號(hào)： | APL5332KAC-TRL |
| 廠商： | Anpec Electronics Corporation |
| 英文描述： | Silver Mica Capacitor; Capacitance:33000pF; Capacitance Tolerance:+/- 1%; Series:CD30; Voltage Rating:100VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:11.1mm; Leaded Process Compatible:No RoHS Compliant: No |
| 中文描述： | CMOS低壓與源庫(kù) |
| 文件頁(yè)數(shù)： | 10/17頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | APL5332KAC-TRL |
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Copyright
ANPEC Electronics Corp.
Rev. A.3 - Oct., 2003
APL5332
www.anpec.com.tw
10
Application I nformation
Layout and Thermal Consideration
The input capacitors are normally placed near VIN for
good performances. Ceramic decoupling capacitors
for load must be placed as close to the load to re-
duce the parasitic inductors of traces. It is also rec-
ommended that the APL5332 and output capacitors
are placed near the load for good load regulation and
transient response. The negative pins of the input and
output capacitors and the GND pin of the APL5332
are connected to analog ground plane of the load.
See Figure 1. The SOP-8-P is a cost-effective pack-
age featuring a small size as a standard SOP-8 and
a bottom thermal pad to minimize the thermal resis-
tance of the package, being applicable to high cur-
rent applications. The thermal pad of SOP-8-P or TO-
252-5 is soldered to the top ground pad which is con-
nected to the internal or bottom ground plane by sev-
eral vias. The printed circuit board (PCB) forms a heat
sink and dissipates major heat into ambient air.
Thermal resistance consists of two main elements,
θ
JC
(junction-to-case thermal resistance) and
θ
CA
(case-
to-ambient thermal resistance).
θ
JC
is specified from
the IC junction to the bottom of the thermal pad di-
rectly below the die.
θ
CA
is the resistance from the
bottom of thermal pad to the ambient air and it
in-
cludes
θ
CS
(case-to-sink thermal resistance) and (sink-
to-ambient thermal resistance). The specified path for
heat flow is the lowest resistance path and it dissipates
major heat to the ambient air. Normally
θ
CA
is major re-
sistance in the path. Enlarging the internal or bottom
ground plane reduces the resistance
θ
CA
. The relation-
ship between power dissipation and temperatures is
P
D
= (T
J
- T
A
) /
θ
JA
where,
P
D
: power dissipation
T
J
: Junction Temperature
T
A
: Ambient Temperature
θ
JA
: Junction-to-Ambient Thermal Resistance
Thermal pad
Die
Top
ground
pad
Printed
circuit
board
Internal
ground
plane
Vias
Ambient
Air
118 mil
102 mil
SOP-8-P
Figure 1
Figure 2 shows a recommended board layout using
the SOP-8-P package. An area of 140mil*110mil on
the top layer (250mil*250mil) is used as a thermal
pad for APL5332 and is connected to the internal or
bottom ground plane by vias. The vias shold have proper
hole size to retain solder, and help heat conduction.
More area of the internal or bottom plane reduces
θ
JA
and is better for dissipating power. The recommended
area is without limit. Therefore the PCB and all com-
ponents form a heat sink.
2
250mil
140mil
1
Internal or bottom
Ground plane
Top layer
ground plane
Soldering area
for bottom pad
Pad
Vias
1
2
3
4
8
7
6
5
Figure 2
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