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參數(shù)資料
| 型號： | APE2901G-33 |
| 廠商： | ADVANCED POWER ELECTRONICS CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 150 kHz SWITCHING FREQ-MAX, PSSO3 |
| 封裝： | LEAD FREE, SOT-89, 3 PIN |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 364K |
| 代理商： | APE2901G-33 |
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
Figure 15. Compound FIFO Expansion
R, W, RS
Q9-Q17
3033 drw 17
IDT
72V01/72V02/72V03/
72V04/72V05/72V06
DEPTH
EXPANSION
BLOCK
Q0-Q8
D9-D17
D0-D8
D0-DN
Q(N-8)-QN
D(N-8)-DN
IDT
72V01/72V02/72V03/
72V04/72V05/72V06
DEPTH
EXPANSION
BLOCK
IDT
72V01/72V02/72V03/
72V04/72V05/72V06
DEPTH
EXPANSION
BLOCK
TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs
Internal Status
Outputs
Mode
RS
FL
XI
Read Pointer
Write Pointer
EF
FF
Reset First Device
0
(1)
LocationZero
0
1
Reset All Other Devices
0
1
(1)
LocationZero
0
1
Read/Write
1
X
(1)
X
NOTE:
1.
XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,
XI = Expansion Input, HF = Half-Full Flag Output
Figure 14. Block Diagram of 1,536 x 9, 3,072 x 9, 6,144 x 9, 12,288 x 9, 24,576 x 9 and 49,152 x 9 FIFO Memory (Depth Expansion)
D
W
IDT
72V01
72V02
72V03
72V04
72V05
72V06
FF
EF
FL
XO
RS
FULL
EMPTY
VCC
R
9
XI
9
Q
FF
EF
FL
XO
XI
FF
EF
FL
XO
XI
IDT
72V01
72V02
72V03
72V04
72V05
72V06
IDT
72V01
72V02
72V03
72V04
72V05
72V06
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
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